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2019-11-01arc: emsdp: docs: Prefer Degilent over Opella-XDAlexey Brodkin
Back in the day on early board samples built-in Digilent JTAG probe was not functional so we used externally attached Ashling Opella-XD probe. But now with production units everything works as expected and so we anybody may enjoy readily avaialble built-in JTAG probe so we specify Digilent oprion on MDB's command line example. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-11-01arc: emsdp/iotdk: Switch to DM_MMCAlexey Brodkin
Somehow EMSDP & IoT DK boards were skipped on ARC boads conversion to DM MMC. So doing it now. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-09-03arc: emsdp: Add more platform-specific compiler optionsAlexey Brodkin
Even though EM SDP is FPGA-based board and different FPGA images (known as .bit-files) are awailable for the board still there's a common subset of options we may rely on for all configs. These are: * Normalizer * Swap instructions * Simple multiplier * Barrel-shifter * Floating-point unit * Shorter instructions (code density) This among other improvements allows to compile code with 64-bit divisions, see [1]. [1] https://patchwork.ozlabs.org/patch/1156541/ Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Kever Yang <kever.yang@rock-chips.com>
2019-09-03arc: emsdp: Add initialization of PSRAMAlexey Brodkin
If the "Page Mode" is not enabled on the device, read operations from PSRAM may result in incorrect data. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-08-11env: Move env_get_ulong() to env.hSimon Glass
Move env_get_ulong() over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11env: Move env_set_ulong() to env.hSimon Glass
Move env_set_ulong() over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-18ARC: [plat-axs10x]: migrate to DM_MMCEugeniy Paltsev
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-04-18ARC: [plat-hsdk]: migrate to DM_MMCEugeniy Paltsev
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-03-28hsdk: readme: Suggest getting pyelftools with pipAlexey Brodkin
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Suggested-by: Yunir Salimzyanov <yunir@synopsys.com>
2019-03-28ARC: AXS10x: drop NAND supportEugeniy Paltsev
On AXS10x boards we have non-standard NAND controller which was never really used a lot as there're other much more convenient [as they are standard & removable] persistent media like SD-card and USB mass storage. Moreover after recent changes we face with some NAND controller runtime issues. So instead of keeping support of yet another non-standard peripheral we're dropping its support for good. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-12-03arc: devboards: Implement checkboard()Alexey Brodkin
This allows us to print nice board name on boot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-12-03arc: emsdp: Refactor register and bit accessesAlexey Brodkin
Instead of "base + offset" define all registers right away and access them later via direct defines. Generate bit masks with "BIT" macro. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-12-03arc: emsdp: Read real CPU clock value from hardwareAlexey Brodkin
We do real CPU clock measurement with help of built-in counters. Thus we may accommodate different real clock values that appear in different FPA images instead of relying on something hard-coded in the .dtb. And while at it make make SDIO base address define look similar to others with casting to "(void *)". Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-12-03arc: Get rid of board-specific print_cpuinfo()Alexey Brodkin
Since we now do advanced CPU identification in generic ARC code there's no need to have per-board hardcoded data. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-11-01iot_dk: Add READMEAlexey Brodkin
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-11-01emdk->emsdp: Rename boardAlexey Brodkin
Real marketing name of the board was recently updated so to accommodate that change renaming the board and all related to it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-12axs10x/emdk/hsdk/iot_dk: Implement board_mmc_getcd()Alexey Brodkin
So now we may detect MMC/SD-card existence and instead of completely misleading message on missing card: ------------------------>8----------------------- Loading Environment from FAT... Card did not respond to voltage select! ------------------------>8----------------------- we now get very clear one: ------------------------>8----------------------- Loading Environment from FAT... MMC: no card present ------------------------>8----------------------- Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-12iot_dk: Save CPU clock value to gd->cpu_clkAlexey Brodkin
Since gd->cpu_clk is a global item we may once populate it from .dtb ans use it then in other places like for printing CPU info etc. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-12iot_dk: Add support of 136 MHz clockAlexey Brodkin
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-12iot_dk: Implement board resetAlexey Brodkin
It is done by writing some magic sequence in a special register. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-12iot_dk/hsdk: Implement its own print_cpuinfo()Alexey Brodkin
ARC IDENTITY register only encodes major architecture type and version while for a particular board/silicon we may know better which template was used and so we may identify CPU more precise, which exactly we do here. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05arc: Add support for IoT development kitAlexey Brodkin
The DesignWare ARC IoT Development Kit is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. More information is avaialble here [1] and here [2]. The board is based on real silicon with ARC EM9D-based Data Fusion IP Subsystem. It sports a rich set of I/O including * DW USB OTG * DW MobileStorage (used for micro SD-card) * GPIO * multiple serial interface including DW APB UART * ADC, PWM and eFlash, SRAM and SPI Flash memory * Real-Time Clock (RTC) * Bluetooth module with worldwide regulatory compliance (FCC, IC, CE, ETSI, TELEC) * On-board 9-axis sensor (gyro, accelerometer and compass) Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18 extension header. One of the most interesting features for developers is built-in Digilent USB JTAG probe so only micro-USB cable is needed! [1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit [2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdf Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31HSDK: Fixes and improvements in READMEAlexey Brodkin
1. Explained prerequisites for "make bsp-generate" command. 2. Cleaned-up duplicates Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31ARC: AXS10x/HSDK: Use our own version of mkimageAlexey Brodkin
Since U-Boot tools are being built anyways it's much nicer to use them instead of relying on some of them bein installed on build host (which might easily not be the case). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31ARC: AXS10x: add tool and make target to generate bspEugeniy Paltsev
AXS10x boards have preloader that reads SPI flash pages and searches special image header to fetch and load binary. Add tool, make target (bsp-generate) to generate update script and u-boot binary image with header for preloader. Also add script to default environment to apply updates. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-06-21ARC: EMDK: Add readmeAlexey Brodkin
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-06-15ARC: HSDK: Add readmeAlexey Brodkin
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-06-15ARC: HSDK: Add tool and make target to generate bspEugeniy Paltsev
HSDK board has preloader that reads SPI flash pages and searches for a special image header to fetch and load binary. Add tool, make target (bsp-generate) to generate update script and u-boot binary image with header for preloader. Also add script to default environment to apply updates. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-05-31ARC: Add support for EM Development Kit boardAlexey Brodkin
Synopsys DesignWare ARC EM Development Kit (ARC EMDK) is an FPGA-based development platform from Synopsys aimed to speed-up development of software for ARC EM cores and entire subsystems based on ARC EM like Data Fusion, Secure and Sensor & Control subsystems. U-Boot is supposed to be used as a primary bootloader on EMDK allowing users to easily load and start their application from micro-SD card. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-02ARC: HSDK: Add platform-specific commandsEugeniy Paltsev
This patch add support of hsdk platform-specific commands: hsdk_clock set - set clock from axi_freq, cpu_freq and tun_freq environment variables/command line arguments hsdk_clock get - save clock frequencies to axi_freq, cpu_freq and tun_freq environment variables hsdk_clock print - show CPU, AXI, DDR and TUNNEL current clock frequencies. hsdk_clock print_all - show all currently used clock frequencies. hsdk_init - setup board HW in one of pre-defined configuration (hsdk_hs34 / hsdk_hs36 / hsdk_hs36_ccm / hsdk_hs38 / hsdk_hs38_ccm / hsdk_hs38x2 / hsdk_hs38x3 / hsdk_hs38x4) hsdk_go - run baremetal application on hsdk configured by hsdk_init command. This patch changes default behaviour of 'bootm' command: now we are able to set number of CPUs to be kicked by setting 'core_mask' environment variable before 'bootm' command run. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-23ARC: bootm: Refactor GO and PREP subcommands implementationEugeniy Paltsev
Refactor GO and PREP subcommands implementation for a simpler override in the boards platform code. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-11ARC: HSDK: Fixup DW SDIO CIU frequency to 50000000HzEugeniy Paltsev
DW SDIO controller has external CIU clock divider controlled via register in the SDIO IP. Due to its unexpected default value (we expected it to divide by 1 but in reality it divides by 8) SDIO IP uses wrong CIU clock (it should be 100000000Hz but actual is 12500000Hz) and works unstable (see STAR 9001204800). So increase SDIO CIU frequency from actual 12500000Hz to 50000000Hz by switching from the default divisor value (div-by-8) to the minimum possible value of the divisor (div-by-2) in HSDK platform code. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-06-29arc: Add support for HS Development Kit boardAlexey Brodkin
ARC HS Development Kit board is a new low-cost development platform sporting ARC HS38 in real silicon with nice set of features such as: * Quad-core ARC HS38 with 512 kB L2 cache and running @1GHz * 4Gb of DDR (we use only lowest 1Gb out of it now) * Lots of DesigWare peripherals * Different connectivity modules: - Synopsys HAPS HT3 - Arduino-compatible connector - MikroBUS This initial commit supports the following peripherals: * UART (DW 8250) * Ethernet (DW GMAC) * SD/MMC (DW Mobile Storage) * USB 1.1 & 2.0 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-03-31axs103: Support slave core kick-start on axs103 v1.1 firmwareAlexey Brodkin
In axs103 v1.1 procedure to kick-start slave cores has changed quite a bit compared t previous implementation. In particular: * We used to have a generic START bit for all cores selected by CORE_SEL mask. But now we don't touch CORE_SEL at all because we have a dedicated START bit for each core: bit 0: Core 0 (master) bit 1: Core 1 (slave) * Now there's no need to select "manual" mode of core start Additional challenge for us is how to tell which axs103 firmware we're dealing with. For now we'll rely on ARC core version which was bumped from 2.1c to 3.0. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-03-31axs103: Clean-up smp_kick_all_cpus()Alexey Brodkin
* Rely on default pulse polarity value * Don't mess with "multicore" value as it doesn't affect execution In essence we now do a bare minimal stuff: 1) Select HS38x2_1 with CORE_SEL=1 bits 2) Select "manual" core start (via CREG) with START_MODE=0 3) Generate cpu_start pulse with START=1 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-03-24arc: dts: separate single axs10x.dts fileVlad Zakharov
We want to use the same device tree blobs in both Linux and U-Boot for ARC boards. Earlier device tree sources in U-Boot were very simplified and hadn't been updated for quite a long period of time. So this commit is the first step on the road to unified device tree blobs. First of all we re-organize device tree sources for AXS10X boards. As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and AXC003 cpu tiles respectively we add corresponding device tree source files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for cpu tiles and axs101.dts and axs103.dts to represent actual boards. Also we delete axs10x.dts as it is no longer used. One more important change - we add timer device to ARC skeleton device tree sources as both ARC700 and ARCHS cores contain such timer. We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree sources as it is referenced via phandle from timer node in common skeleton.dtsi file. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-05arc: Rename AXS101 board to more generic AXS10xAlexey Brodkin
As of now we have 2 flavors of ARC SDP boards: 1) AXS101 - with ARC770 in ASIC 2) AXS103 - with ARC HS38 in FPGA Both options share exactly the same base-board and only differ with CPU-tiles in use. That means all peripherals are the same (they are implemented in FPGA on the base-board) and so generic board could be used for both. While at it: * Recreated defconfigs with savedefconfig * In include/configs/axs10x.h numerical sizes replaced with defines from linux/sizes.h for better readability. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-05arc: Rename ARCangel4 board to nSIMAlexey Brodkin
ARCangel was one of the main development boards back in the day but now it's gone and replaced by other boards like ARC SDP. But we also used to have simulation platform very similar to ARCangel4 in terms of CPU settings as well as basic IO like UART. Even though ARCangel4 is long gone now we have a replacement for simulation which is a plain or stand-alone nSIM and Free nSIM. Note Free nSIM is available for download here: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi And while at it: * Finally switch hex numerical values in nsim.h to defines from include/linux/sizes.h * Add defconfigs with ARC HS38 cores * Recreated all defconfigs with savedefconfig Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-06-13board: axs10x: Flush entire cache after programming reset vectorAlexey Brodkin
Now when we have support of IOC (IO-Coherency block) cahce operations on regions are tuned to not be dummy stubs if IOC was found and enabled in the core. That makes flush_dcache_range() useless for our purposes here. And since we do need to flush modified reset vector to at least L2 cache (AKA SLC) so other cores will see it via its L1 instruction cache we're using always functional flush_dcache_all() here. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Marek Vasut <marex@denx.de>
2015-11-18board: axs10x switch serial port and Ethernet to driver modelAlexey Brodkin
With this change Synopsys DesignWare SDP board is switched to driver model for both serial port (serial_dw) and Ethernet (Designware GMAC). This simplifies include/configs/axs101.h and allows for reuse of Linux's Device Tree description. For simplicity Linux's .dts files are not blindly copied but only very few extracts of them are really used (those that are supported in U-Boot at the moment). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-10-07board: axs10x - cap max SDIO clock value to bus/2Alexey Brodkin
It turned out with some boards (FPGA firmwares?) and cards combos current clock settings doesn't work as expected leading to strange card freezes or corrupted data being read from the card. Especially this was seen with Transcend 2Gb cards shipped as a part of ARC SDP: ----------------->8--------------- AXS# mmcinfo Device: Synopsys Mobile storage Manufacturer ID: 74 OEM: 4a60 Name: SDC Tran Speed: 50000000 Rd Block Len: 512 SD version 3.0 High Capacity: No Capacity: 1.8 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes AXS# fatload mmc 0 ** Unrecognized filesystem type ** ----------------->8--------------- With this change that problem is fixed. Note "Tran Speed" above doesn't match clock value set in DW MMC. It is max value for card's speed class. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-07-01board: axs103 - add maintainer informationAlexey Brodkin
Looks like I forgot to add myself as a maintainer for AXS103 defconfig. Fixing this now. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@konsulko.com>
2015-07-01arc: implement slave cores kick-start for Linux kernelAlexey Brodkin
With new SMP-enabled CPUs with ARC HS38 cores and corresponding support in Linux kernel it's required to add basic SMP support in U-Boot. Currently we assume the one and only core starts execution after power-on. So most of things in U-Boot is handled in UP mode. But when U-Boot is used for loading and starting Linux kernel right before jumping to kernel's entry point U-Boot: [1] Sets all slave cores to jump to the same address [kernel's entry point] [2] Really starts all slav cores In ARC's implemetation of SMP in Linux kernel all cores are supposed to run the same start-up code. But only core with ID 0 (master core) processes further while others are looping waiting for master core to complete some initialization. That means it's safe to un-pause slave cores and let them execute kernel - they will wait for master anyway. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com>
2015-04-09board: axs10x - support v3 mother-boardAlexey Brodkin
There're 2 versions of motherboards that could be used in ARC SDP. The only important difference for U-Boot is different NAND IC in use: [1] v2 board (we used to support up until now) sports MT29F4G08ABADAWP while [2] v3 board sports MT29F4G16ABADAWP They are almost the same except data bus width 8-bit in [1] and 16-bit in [2]. And for proper support of 16-bit data bus we have to pass NAND_BUSWIDTH_16 option to NAND driver core - which we do now knowing board type we're running on. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-04-03board: AXS10x - update SDIO clock valueAlexey Brodkin
With the most recent board firmware correct SDIO clock is 50MHz as opposed to 25 MHz before. Also set max frequency of MMC data exchange equal to SDIO clock - because there's no way to transfer data faster than interface clock. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: add selection of endianess in KconfigAlexey Brodkin
This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-01-15board/synopsys: remove selection of CPU from the boardAlexey Brodkin
Both ARCangel4 and AXS10x are FPGA-based boards so they may have different CPUs. For now we have only 1 option (ARC700) and we define this as default in arch Kconfig. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2014-09-13kconfig: remove redundant "string" type in arch and board KconfigsMasahiro Yamada
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-26axs101: Fix type mismatch warningVasili Galka
Initialization of pointer from integer shall be designated by explicit type cast. Signed-off-by: Vasili Galka <vvv444@gmail.com> Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
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