summaryrefslogtreecommitdiff
path: root/board/xilinx/versal/board.c
AgeCommit message (Collapse)Author
2019-02-14arm64: versal: Move IOU_SWITCH_DIVISOR0 to KconfigMichal Simek
Move hardcoded IOU_SWITCH_DIVISOR0 to Kconfig to be able to set it up for different platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14arm64: versal: Remove one level of indentation in board_early_init_r()Michal Simek
Simplify code indentation. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>