| Age | Commit message (Collapse) | Author |
|---|
|
|
|
Now the DDR2 frequency is also 2*PLB frequency when 166MHz PLB
is selected.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
The board specific "bootstrap" command is now fixed and can
be used for the AMCC Katmai board to configure different
CPU/PLB/OPB frequencies.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
|
|
|
|
This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
This patch cleans up all the open issue of the preliminary
Acadia support.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
(Dot outside sections problem).
This fix is in the spirit of 807d5d7319330e336ab34a5623c5e0d73b87d540.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
|
|
|
|
|
|
|
|
|
This patch adds support for the new AMCC Acadia eval board.
Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
for the SIUMCR and BCR Register.
Fix the calculation for the EEprom Size
Signed-off-by: Heiko Schocher <hs@denx.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
(SC3 and Jupiter used to use 'addcon' instead).
Signed-off-by: Wolfgang Denk wd@denx.de
|
|
|
|
|
|
|
|
support
|
|
|
|
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>
|
|
|
|
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
|
|
|
|
|
|
|
|
The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.
This patch also enables the cache in FLASH for the startup
phase of U-Boot (while running from FLASH). After relocating to
SDRAM the cache is disabled again. This will speed up the boot
process, especially the SDRAM setup, since there are some loops
for memory testing (auto calibration).
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
|
|
Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
|
|
|
|
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.
For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
(cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit)
|
|
Disable G1TXCLK, G2TXCLK h/w buffers. This patch
fixes a networking timeout issue with MPC8360EA (Rev.2) PBs.
Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Emilian Medve <Emilian.Medve@freescale.com>
|
|
The code supply fixed and SPD initialization for MPC83xx DDR2 Controller.
it pass DDR/DDR2 compliance tests.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
|
|
Add support for the MPC8349E-mITX-GP, a stripped-down version of the
MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in
HRCW is 0) for the ITX and a README for the ITX and the ITX-GP.
Signed-off-by: Timur Tabi <timur@freescale.com>
|
|
There is no SDRAM on any of the 8349 ITX variants, so function sdram_init()
never does anything. This patch deletes it.
Signed-off-by: Timur Tabi <timur@freescale.com>
|
|
I've redone the SBC8349 support to match git-current, which
incorporates all the MPC834x updates from Freescale since the 1.1.6
release, including the DDR changes.
I've kept all the SBC8349 files as parallel as possible to the
MPC8349EMDS ones for ease of maintenance and to allow for easy
inspection of what was changed to support this board. Hence the SBC8349
U-Boot has FDT support and everything else that the MPC8349EMDS has.
Fortunately the Freescale updates added support for boards using CS0,
but I had to change spd_sdram.c to allow for board specific settings for
the sdram_clk_cntl (it is/was hard coded to zero, and that remains the
default if the board doesn't specify a value.)
Hopefully this should be mergeable as-is and require no whitespace
cleanups or similar, but if something doesn't measure up then let me
know and I'll fix it.
Thanks,
Paul.
|
|
A redundant semicolon existed in mpc8349itx.c
should be removed.
Signed-off-by: Sam Song <samsongshu@yahoo.com.cn>
|
