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1) Add new SerDes1 protocols having Aurora in them
2) Add VSC cross point connections for Aurora to work with
CPRI and SGMIIs
3) Configure VSC crossbar switch to connect SerDes1
lanes to aurora on board, by checking SerDes1 protocols
4) SerDes1 Refclks have been set properly to make
Aurora, CPRI and SGMIIs to work together properly
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Before this commit, CONFIG_MPC8260 and CONFIG_8260
were used mixed-up.
All boards with mpc8260 cpu defined both of them:
- CONFIG_MPC8260 was defined in board config headers
and include/common.h
- CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk
We do not need to have both of them.
This commit keeps only CONFIG_MPC8260.
This commit does:
- Delete CONFIG_8260 and CONFIG_MPC8260 definition
in config headers and include/common.h
- Rename CONFIG_8260 to CONFIG_MPC8260
in arch/powerpc/cpu/mpc8260/config.mk.
- Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
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Many (but not all) of Blackfin boards give -O2 option
to compile under lib/ directory.
That means lib/ should be speed-optimized,
whereas other parts should be size-optimized.
We want to keep the same behavior,
but do not want to parse board/*/config.mk again and again.
We've got no choice but to invent a new method.
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED, if it is enabled,
gives -O2 flag only for building under lib/ directory.
Dirty codes which I had marked as "FIX ME"
in board/${BOARD}/config.mk have been deleted.
Instead, CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED has been
defined in include/configs/${BOARD}.h.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
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As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.
This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tirumala Marri <tmarri@apm.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
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config.tmp is never generated
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
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B&R boards are using Phy Addresses 'one' and 'two', prior this was
defined through #define PHYADDR 1 within a header file.
Now this is addresses are given with device-driver structure.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
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Include <input.h> in order to fix the following sparse warning:
wandboard.c:278:5: warning: symbol 'overwrite_console' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Add a prototype for board_phy_config() to fix the following sparse warning:
wandboard.c:200:5: warning: symbol 'board_phy_config' was not declared. Should it be static?
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Fix the following sparse warning:
wandboard.c:58:22: warning: symbol 'usdhc1_pads' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5
Signed-off-by: Pekon Gupta <pekon@ti.com>
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There are no source files in board/synopsys/arcangel4/
directory.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
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config.tmp is not there.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Ignore
- board/cray/L1/bootscript.{c|image}
- board/matrix_vision/mvblm7/bootscript.img
- board/maxtir_vision/mvsmr/bootscript.img
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
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The same outputs are generated with or without -I$(TOPDIR)/board.
I cannot understand why it is necessary. Remove.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
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Convert sandbox over to use driver model GPIOs.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini <trini@ti.com>
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Since the switch may be re-configured for VLAN usage in Linux (or any
other OS), lets reset the switch to its default register values upon
power-up. Otherwise network might not be available in U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Lukas Stockmann <lukas.stockmann@siemens.com>
Cc: Tom Rini <trini@ti.com>
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Add Ethernet Boot support to SPL
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
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Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like
400MHz the read latency expected will be CL+3 as per tests from HW
folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team
to come back for better explanation).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Adding support for reading cpsw 2nd mac address from efuse and pass it
to kernel via dtb which will be used in dual emac mode of cpsw.
Also correct the bit masking of mac id read from the efuse.
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
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Adding support for reading cpsw 2nd mac address from efuse and pass it
to kernel via dtb which will be used in dual emac mode of cpsw.
Also adding mii command support to am335x common config.
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
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Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected
to RMII and RGMII phy respectively and enable cpsw in config.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
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Some platforms like AM437x have different EVMs with different phy addresses,
so this patch adds support for passing phy address via cpsw plaform data.
Also renamed phy_id to phy_addr so better understanding of the code.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335
pengwyn boards]
Signed-off-by: Tom Rini <trini@ti.com>
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board/sheldon/simpc8313/config.mk is used only for nand_spl.
So it should go into nand_spl/board/sheldon/simpc8313/.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Read ram size directly from DTB.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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NAND boot mode on AM335x EVM has been verified, and steps
to use it has been documented and update in this README
Signed-off-by: Pekon Gupta <pekon@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Acked-by: Tom Rini <trini@ti.com>
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Conflicts:
arch/arm/cpu/armv7/config.mk
board/ti/am43xx/mux.c
include/configs/am43xx_evm.h
Signed-off-by: Tom Rini <trini@ti.com>
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Remove the last uses of symbol offsets in ARM U-Boot.
Remove some needless uses of _TEXT_BASE.
Remove all _TEXT_BASE definitions.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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This prevents references to _end from generating absolute
relocation records.
This change is binary invariant for ARM targets.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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Newly added cm_t335 was missed in commit 47ed5dd0 which
made ARM targets produce full ELF files. Fix its linker
script.
This change is binary-invariant when only .dynsym, .dynstr,
.dynamic, .plt, .interp and .gun sections are declared.
Sections .hash, .got.plt, .dynbss and .ARM.exidx are also
declared so that their (unused) content is moved out of the
u-boot binary.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.c
Signed-off-by: Tom Rini <trini@ti.com>
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Rename OBJCFLAGS to OBJCOPYFLAGS beforehand to use
"cmd_objcopy" in scripts/Makefile.lib in an upcoming commit.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.
For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.
This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.
T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
- Two on-board 10M/100M/1G bps RGMII ports
- Two 10Gbps XFI with on-board SFP+ cage
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
- Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
- 8 lanes up to 10.3125GHz
- Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
- 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
- Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
voltage translators
- I2C:
- Four I2C controllers.
- UART:
- Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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HOSTCFLAGS_autoconf.mk.dep was added by commit 422322f
but it has never been used.
Cc: Vadim Bendebury <vbendeb@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Add support for the bcm28155_ap reference board.
Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Tim Kryger <tkryger@linaro.org>
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New hardware version cannot recognize the SD-Card
because the SYS_NRESWARM, set as GPIO, does not
guarantee the required reset time.
Change the pin function back to enable the
SYS_NRESWARM signal driven by the SOC.
Signed-off-by: Stefano Babic <sbabic@denx.de>
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Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[trini: Rework patch against mainline]
Signed-off-by: Tom Rini <trini@ti.com>
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Adds support for Bernecker & Rainer Industrieelektronik GmbH KWB
Motherboard, using TI's AM3352 SoC.
Most of code is derived from TI's AM335x_EVM
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: trini@ti.com
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Adds support for Bernecker & Rainer Industrieelektronik GmbH T-Series
Motherboard, using TI's AM3352 SoC.
Most of code is derived from TI's AM335x_EVM
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
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This patch add support for the Silica Pengwyn board [1]
The board is based on a TI AM3354 CPU [2]
All jumpers removed it will boot from the SDcard, the console is on
UART1 accessible via the FDTI -> USB. The on board NAND flash is
supported and can act as boot medium, depending on jumper settings.
USB Host, USB Device and Ethernet are also provided but untested.
[1]
http://www.silica.com/product/silica-pengwyn-board.html
[2]
http://www.ti.com/product/am3354
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
[trini: Move CONFIG_BOARD_LATE_INIT into am335x_evm.h, drop unused
spi0_pin_mux from Pengwyn support]
Signed-off-by: Tom Rini <trini@ti.com>
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This function has been around for powerpc. It is used for systems with
memory more than CONFIG_MAX_MEM_MAPPED. In case of non-contiguous memory,
this feature can limit U-boot to one block without going over the limit.
Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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With accepted change to DW GMAC driver -
92a190aaab3536d695c51e0739f925910eb49889 (net/designware - switch driver
to phylib usage) we need to update this board because
"designware_initialize" now accepts only 2 parameters instead of 4.
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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With d6a320d we moved some clock externs out of blackfin_local.h and
into clock.h but now need to include <asm/clock.h> in more drivers to
avoid warnings.
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Tom Rini <trini@ti.com>
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Commit 5ab502cb gathered all device tree sources
to arch/$(ARCH)/dts/.
So tegra124-venice2.dts also must go to arch/arm/dts directory
to build venice2 board.
(Commit 5ab502cb had been posted before venice2 board support
was merged. So an unvisible conflict happened.)
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
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