| Age | Commit message (Collapse) | Author |
|---|
|
Conflicts:
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
|
Some eMMC chips may need the RST_n_FUNCTION bit set to a non-zero value
in order for warm reset of the system to work. Details on this being
required will be part of the eMMC datasheet. Also add using this
command to the dra7xx README.
* Whitespace fix by panto
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
The DRAM size can be easily detected at runtime on i.MX53. Implement
such detection on M53EVK and adjust the rest of the macros accordingly
to use the detected values.
An important thing to note here is that we had to override the function
for trimming the effective DRAM address, get_effective_memsize(). That
is because the function uses CONFIG_MAX_MEM_MAPPED as the upper bound of
the available DRAM and we don't have gd->bd->bi_dram[0].size set up at
the time the function is called, thus we cannot put this into the macro
CONFIG_MAX_MEM_MAPPED . Instead, we use custom override where we use the
size of the first DRAM block which we just detected.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
|
|
The DRAM size can be easily detected at runtime on i.MX53. Implement
such detection on MX53QSB and adjust the rest of the macros accordingly
to use the detected values.
An important thing to note here is that we had to override the function
for trimming the effective DRAM address, get_effective_memsize(). That
is because the function uses CONFIG_MAX_MEM_MAPPED as the upper bound of
the available DRAM and we don't have gd->bd->bi_dram[0].size set up at
the time the function is called, thus we cannot put this into the macro
CONFIG_MAX_MEM_MAPPED . Instead, we use custom override where we use the
size of the first DRAM block which we just detected.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
|
|
Add support for PCIe on MX6 SabreSDP board and enable the support
in the config file.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Liu Ying <Ying.Liu@freescale.com>
|
|
Enable USB0 clock by resetting bit 20 of MSTPCR2. Leave other bits unchanged.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
|
All pins should be output.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
|
If we build this function in cases where we would be discarding it
anyhow we still end up with maybe unused warnings. Rather than litter
the function with __maybe_unused, just spell out when to build it.
Signed-off-by: Tom Rini <trini@ti.com>
|
|
CPU sets DMA buffer descriptors with data required for inetrnal DMA such as:
* Ownership of BD
* Buffer size
* Pointer to data buffer in memory
Then we need to make sure DMA engine of NAND controller gets proper data.
For this we flush buffer rescriptor.
Then we're ready for DMA transaction.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
|
|
U-Boot uses the 'mkimage' tool to produce various image types,
not only uImage image type. Rename the invocation name from
UIMAGE to MKIMAGE.
The following command was used to do the replacement:
git grep 'quiet_cmd_mkimage.* = UIMAGE' | cut -d : -f 1 | \
xargs -i sed -i "s@\(quiet_cmd_mkimage\)\(.*\) = UIMAGE @\1\2 = MKIMAGE@" {}
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
|
|
I2C protocol requires open-drain IOs. Fix the Dalmore and Venice2 pinmux
tables to configure the IOs correctly. Without this, Tegra may actively
drive the lines high while an external device is actively driving the
lines low, which can only lead to bad things.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.
Conflicts:
board/samsung/common/board.c
|
|
Add a simple LCD driver which uses SDL to display the image. We update the
image regularly, while still providing for reasonable performance.
Adjust the common lcd code to support sandbox.
For command-line runs we do not want the LCD to be displayed, so add a
--show_lcd option to enable it.
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
Add board code to set up the Chrome OS EC on startup.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
Add a common library for obtaining access to the Chrome OS EC. This is
used by boards which need to talk to the EC.
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Tested-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
romImage is set by CONFIG_ECOVEC_ROMIMAGE_ADDR to 0xA0040000.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
|
|
|
|
|
Prior to Kbuild, $(TOPDIR) or $(SRCTREE) was used for
pointing to the top of source directory.
(No difference between the two.)
In Kbuild style, $(srctree) is used for instead.
This commit renames SRCTREE to srctree and deletes the
defition of SRCTREE.
Note that SRCTREE in scripts/kernel-doc, scripts/docproc.c,
doc/DocBook/Makefile should be keep.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
|
|
Prior to Kbuild, $(TOPDIR) or $(SRCTREE) was used for
pointing to the top of source directory.
(No difference between the two.)
In Kbuild style, $(srctree) is used instead.
This commit renames TOPDIR to srctree and delete the
defition of TOPDIR.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
|
|
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: David Updegraff <dave@cray.com>
Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
|
|
- fix: return-value of 'i2c_set_bus_speed' was interpreted wrong
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
|
|
The switch HW reset results in a disconnection of the switch port daisy-
chain for a few seconds. This is not desired in the normal field use
case. So lets remove this switch reset from the normal bootup sequence
and move it into a board specific command. This way it can be executed
in the development environment when really needed.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Lukas Stockmann <lukas.stockmann@siemens.com>
Cc: Tom Rini <trini@ti.com>
|
|
This patch enables to run Trats2 board on device tree.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
|
|
This patch enables to run Trats board on device tree.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
|
|
This patch enables to run Universal board on device tree.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
|
|
This patch enables to run Origen board on device tree.
Uart, DRAM and MMC init functions are removed as their
generic replacements form the common board file are used.
The config file is modified to contain only board specific options.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
|
|
This patch enables sdhci initialisation and misc_init_r in common board
file for all exynos 4 based boards.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
|
|
This patch moves board specific max77686 init function from
common board to smdk5250 board file.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Cc: Rajeshwari Birje <rajeshwari.birje@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
|
|
This patch adds common dtsi file and config header for all
Exynos 4 based boards.
Patch additionaly adds board specific (weak) functions for
board_early_init_f and board_power_init functions.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
|
|
The checkboard function's implementation is common for all
DT supporting boards and should be placed in the board common file.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Cc: Amar <amarendra.xt@samsung.com>
Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
|
|
Gateworks Ventana is a product family based on the i.MX6. This
patch adds support for all boards in the Ventana family. Where
possible, data from the boards EEPROM is used to determine various
details about the board at runtime.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
|
|
|
|
Many USB host controller drivers contain almost identical copies of the
same virtual root hub descriptors. Put these into a common file to avoid
duplication.
Note that there were some very minor differences between the descriptors
in the various files, such as:
- USB 1.0 vs. USB 1.1
- Manufacturer/Device ID
- Max packet size
- String content
I assume these aren't relevant.
Cc: Thomas Lange <thomas@corelatus.se>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Gary Jennejohn <garyj@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Eric Millbrandt <emillbrandt@coldhaus.com>
Cc: Pierre Aubert <p.aubert@staubli.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: Denis Peter <d.peter@mpl.ch>
Cc: Rodolfo Giometti <giometti@linux.it>
Cc: Zhang Wei <wei.zhang@freescale.com>
Cc: Mateusz Zalega <m.zalega@samsung.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Markus Klotzbuecher <mk@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Gary Jennejohn <garyj@denx.de>
Cc: C Nauman <cnauman@diagraph.com>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Thomas Abraham <t-abraham@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Andrew Murray <amurray@embedded-bits.co.uk>
Cc: Matej Frančeškin <matej.franceskin@comtrade.com>
Cc: Cliff Cai <cliff.cai@analog.com>
Cc: Bryan Wu <cooloney@gmail.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
|
|
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Rob Herring <robh@kernel.org>
|
|
CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it
as 1000000 and idmr.h defines it as (50000000 / 64).
When compiling these two boards, a warning message is displayed:
time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000
and should not be defined by platforms" [-Wcpp]
There are no board maintainers for them so this commit just
deletes them.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jason Jin <Jason.jin@freescale.com>
|
|
Add NAND SPL boot support with hardware PMECC.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
|
|
Add SPI SPL boot support for sama5d3xek board.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
|
|
Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC.
Now it supports boot from NAND flash and SD/MMC card.
Features support:
- NAND flash
- SD/MMC card
- Two USB hosts
- Ethernet (one GMAC, one EMAC)
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[reorder boards.cfg]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
|
|
Add support for using the Atmel MCI driver on at91sam9263ek.
This change is modeled after the existing at91sam9260ek support.
Please note that this hooks up slot1 (MCI1) for SD. Not both.
Tested with at91bootstrap and u-boot on dataflash in slot 0
and fat-formatted 8GB SDHC in slot 1 on first revision
at91sam9263ek (which must use dataflash in slot0 to boot).
CONFIG_ATMEL_MCI_PORTB not tested.
Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se>
[remove empty line]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
|
|
|
|
Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
|
|
T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder
Chrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
|
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.
T2080PCIe-RDB Feature Overview
------------------------------
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
- SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
- SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
- SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
- SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
- SerDes-2 Lane G-H: to SATA1 & SATA2
IFC/Local Bus:
- NOR: 128MB 16-bit NOR flash
- NAND: 512MB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 gold-finger
- One PCIe x4 connector
- One PCIe x2 end-point device (C293 Crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a TF-card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
|
Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0.
Fix EMI2 for t2080qds, which was caused by adding t2081qds.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
|
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration
Both these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
|
Change setting of SerDes2 refclk2 to have the default value as it is
coming on board that is 156.25MHz, for XFI to work.
Also change PLL_NUM variable to the one defined in config_mpc85xx.h
for B4860 and B4420.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
|
On B4860 and B4420, some serdes protocols can be used with LC VCO as
well as Ring VCO options.
Addded Alternate options with LC VCO for such protocols.
For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO.
The alternate option has the same functionality as the original option;
the only difference being LC VCO rather than Ring VCO.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
|
1) SerDes2 Refclks have been set properly to make
PCIe SATA to work as it work on SerDes refclk of 100MHz
2) Mask the SerDes's device reset request before changing
the Refclks for SerDes1 and SerDes2 for PLL locks to
happen properly, device reset request bit unmasked
after SerDes refclks configuration
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
