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Remove not needed pci_target_init() function.
Signed-off-by: Stefan Roese <sr@denx.de>
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Disabled and remove inka4x0 custom flash driver, use CFI flash
driver instead.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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Add support for three new DDR chips that may be present on a NG
INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT.
Cleanup board/inka4x0/mt48lc16m16a2-75.h file.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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- Cleanup compile warnings.
- Add missing '\0' in default environment.
- Increase CFG_MONITOR_LEN to 256 KiB.
- Add required CFG_USE_PPCENV.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
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Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
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Add cfb console support to FSL 8610 DIU driver.
Inspect board version from PIXIS to obtain correct pixel format.
Use #define CONFIG_VIDEO in config file to enable fb console.
To switch monitor, set monitor variable to
0 - DVI, 1 - Single link LVDS, 2 - Double link LVDS
followed by "diufb init".
Preserve logo bitmap at the top of the fb console.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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1280x1024 and 1024x768 @ 32 bpp are supported now.
DVI, Single-link LVDS, Double-link LVDS are all supported.
Environmental variable "monitor" is used to specify monitor port.
A new command "diufb" is introduced to reinitialize monitor
and display a BMP file in the memory. So far, 1-bit, 4-bit,
8-bit and 24-bit BMP formats are supported.
diufb init
- initialize the diu driver
Enable the port specified in the environmental variable "monitor"
diufb addr
- display bmp file in memory.
The bmp image should be no bigger than the resolution, 1280x1024
for DVI and double-link LVDS, 1024x768 for single-link LVDS.
Note, this driver allocate memory but doesn't free it after use
It is written on purpose -- to avoid a failure of reallocation
due to memory fragement.
ECC of DDR is disabled for DIU performance. L2 data cache is also disabled.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon loeliger <jdl@freescale.com>
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This Freescale logo is a 340 x 128 x 4bpp BMP file
that can be displayed by the DIU Framebuffer driver.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Now not max 3 lines but 2 lines are printed per PCIe port.
Signed-off-by: Stefan Roese <sr@denx.de>
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usb_cpu_init() configures GPS USB pins, clocks, etc. and
is required for proper operation of kernel USB subsystem.
This setup was previously done in the kernel by the fixup
code which is being removed, thus low level init must be
done by U-boot now.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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To get the IDS8247 board working following are done:
- FCC2 is deactivated
- FCC1 is activated
- I2C is activated
- CFI driver is activated
- Adapted for use with LIBFDT
Signed-off-by: Sergej Stepanov <Sergej.Stepanov@ids.de>
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This patch adds NAND booting support for the AMCC 405EX(r) eval boards.
Again, only one image supports both targets.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
and to the Sequoia TLB init code. Now the cache can be enabled on 44x
boards by defining CONFIG_4xx_DCACHE in the board config file. This
option will disappear, when more boards use is successfully and no
more known problems exist.
This is tested successfully on Sequoia and Katmai. The only problem that
needs to be fixed is, that USB is not working on Sequoia right now, since
it will need some cache handling code too, similar to the 4xx EMAC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
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The Haleakala is nearly identical with the Kilauea eval board. The only
difference is that the 405EXr only supports one EMAC and one PCIe
interface. This patch adds support for the Haleakala board by using
the identical image for Kilauea and Haleakala. The distinction is done
by comparing the PVR.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:
Note:
As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
modules are still plugged in. So it is recommended to remove the DIMM
modules while using the NAND booting code with the fixed SDRAM setup!
Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Change all linker scripts to reference the changed driver name iop480_uart.o.
Signed-off-by: Stefan Roese <sr@denx.de>
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Change all linker scripts to reference the changed driver name 4xx_uart.o.
Note: In most cased all these explicit referencing of these object files
in the linker scripts is not neccessary. Only for manually embedded
environment into the U-Boot image, which is not done is most cases.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.
Lot's of other macros are good candidates to be consolidated this way
in the future.
Signed-off-by: Stefan Roese <sr@denx.de>
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The size was initilized wrong. Instead of 256MB, the DDR2 controller
was setup to 512MB. Now the correct values is used.
This patch also does a little cleanup and adds a comment here.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.
This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:
pcie_mode=RP:EP:EP
This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.
Per default Yucca will be configured as:
pcie_mode=RP:EP:EP
Per default Katmai will be configured as:
pcie_mode=RP:RP:REP
Per default Kilauea will be configured as:
pcie_mode=RP:RP
Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch enables the fdt support on the AMCC Kilauea eval board.
Additionally now EBC ranges fdt fixup is included to support NOR
FLASH mapping via the Linux physmap_of driver.
This Kilauea port now support booting arch/ppc and arch/powerpc
Linux kernels. The default environment "net_nfs" is for arch/ppc
and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
support will be removed.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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These files were introduced with the IBM 405GP but are currently used on all
4xx PPC platforms. So the name doesn't match the content anymore. This patch
renames the files to 4xx_pci.c/h.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(2) This patch renames the functions from 440spe_ to 4xx_ with a
little additional cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(1) This patch renames the files from 440spe_pcie to 4xx_pcie
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
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Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
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grafic controller
Some commands for the STK52xx base board try to access the SM501 grafic
controller. But the TQM5200S has no grafic controller (only the TQM5200
and the TQM5200B have). This patch deactivates the commands accessing
the SM501 for the TQM5200S.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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grafic controller
Some commands for the STK52xx base board try to access the SM501 grafic
controller. But the TQM5200S has no grafic controller (only the TQM5200
and the TQM5200B have). This patch deactivates the commands accessing
the SM501 for the TQM5200S.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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The pxa255_idp being an old unmaintained board showed several issues:
1. CONFIG_INIT_CRITICAL was still defined.
2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
3. Symbol flash_addr was undeclared.
4. The boards lowlevel_init function was still called memsetup.
5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
6. Using -march=armv5 instead of -march=armv5te resulted in lots of
'target CPU does not support interworking' warnings on recent compilers.
7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
indexes rather than the register definitions from the pxa-regs header
file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
avoid any ambiguities.
8. There were several redefinition warnings concerning ICMR, OSMR3,
OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
9. The board configuration file was rather outdated.
10. The part header file defined the vendor, product and revision arrays
as unsigned chars instead of just chars in the block_dev_desc_t
structure.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
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Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
register must be written a value of 0x00000004 as the first step of the
SDRAM contorller configuration.
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
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