| Age | Commit message (Collapse) | Author |
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Fixes a build warning of implicit declaration of
gpio_direction_output, as bellow:
,----
| mx23_olinuxino.c: In function 'board_early_init_f':
| mx23_olinuxino.c:51:2: warning: implicit declaration
| of function 'gpio_direction_output'
| [-Wimplicit-function-declaration]
`----
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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Provide a structure for accessing HDMI registers, so that we can use proper
read/write accessors.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
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This enabled USB support for the mx23_olinuxino board.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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This allow user to know if the bootloader is running, even without a
serial console.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
128MB of RAM.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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The USB port 0 can now be used alongside the USB port 1, thus enable
power to it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
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Rename all i.MX6 pad declarations to MX6_PAD_x, so a board
may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo
(MX6DL) by including the proper header.
Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd
only support MX6Q, so they include mx6q_pins.h.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
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This patch has no functional changes and simply replaces
leading spaces with tabs.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
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This is currently set to coreboot.dtsi, but we cannot support this on
old device tree compilers (dtc <= 1.3), so adjust to use ARCH_CPU_DTS
to let the Makefile preprocessor sort this out.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Board and config header files for bf609-ezkit support.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
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CONFIG_SPL_OS_BOOT_KEY is used only in board files. It is
not required to have a general CONFIG_ option. Rename it and
define it in board directory.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
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Commit 8b710b1 started removing code for the unmaintained "ns9750dev"
board; the board support is still broken, and not included anywhere in
the Makefile or boards.cfg. Remove the remaining dead code.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Add at91sam9g20_2mmc nand boot support. on this board, there is no
dataflash, so disable it
change one commet for at91sam9g20ek board
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Extract FPGA version from the .rbf and pass this info to the kernel.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
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Rather than load the FPGA file from the FAT partition, look
at entry in system EEPROM to decide which file to retrieve directly
from the EXT3 partition.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
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The IGEP COM PROTON is a new ultra compact module design with an
on-board ethernet controller.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
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This trivial patch only changes current boards names for the official
names.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
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This adds necessary config options and a new build target,
am335x_evm_usbspl, to enable usb booting and fixes board_eth_init()
function to take into account that we may have USB ether support in SPL
now. This uses the same MAC for both cpsw and USB, in order to match
ROM behavior.
The usbspl build target does not contain UART SPL, CPSW SPL or extra
environment settings, so that we may fit within our binary size
constraint.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Signed-off-by: Tom Rini <trini@ti.com>
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The pcm051 does not have the wp pin connected to the sd-card socket.
Therefore remove the pinmux for the pin. The was a carry-over from
the am335x evm code.
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
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http://www.lsr.com/wireless-products/com6l
The eeprom on this expansion board requires 16bit addressing.
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
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Some expansion boards now ship with at24 eeproms that need to communicate
via 16bit addressing.
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
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There is no need for a environment variable to configure the dtt bus.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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Replace uImage with ${uimage}.
If uimage is not set, default it to uImage.
Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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kmvect1 has a UEC2 connection to the piggy board and a UEC0 connection
to the switch MV88E6122. This switch has a connection to a frontport
ethernet interface. The ethernet port used for network booting is
automatically selected by u-boot. If a Piggy is plugged, the Piggy
port is selected (UEC2, eth1). If the Piggy isn't present, the
Frontport is selected (UEC0, eth0).
The switch reset is connected to a GPIO on the PRIO3 board FPGA (GPIO28)
and released at startup.
Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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For the the kmvect1 board we will also need a functionality to add an
offset to the IVMs MAC address, because these board will have two valid
ethernet ports for debugging purpose. So move the code to an own
function.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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For kmvect1 we need a special solution and for km_arm boards we already
have. So move the common code to the architectur specific file.
Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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This define isn't set within our setup files. So we can safely remove
the affected code.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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EEprom_ivm_addr isn't set in our environment, so remove the usage of
this.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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All boards from this serie use i2c. There is no need to #ifdef the
header.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
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These are no longer used and should be removed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
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In commit cfd4ff6 we implemented part of advisory 1.0.10 (internal delay
for RGMII mode not supported). This in turn however requires that we
set the tx clock delay feature in the PHY itself.
Signed-off-by: Tom Rini <trini@ti.com>
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All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK
hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to
DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it.
In these conditions:
tRCD(min) = 13.125 ns
tRP(min) = 13.125 ns
tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min)
tRAS(min, DDR3-1333H) = 36 ns
tRAS(min, DDR3-1600K) = 35 ns
MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG0[3:0].
MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded
as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18].
MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG1[2:0].
MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[31:29].
MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[28:26].
MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded
as 0x1A in the bit-field MMDC1_MDCFG1[25:21].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded
as 0x23 for the bit-field MMDC1_MDOR[5:0].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded
as 0x10 for the bit-field MMDC1_MDOR[13:8].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR.
For all DDR3 speed bins:
tXPR(min) = max(5 nCK, tRFC(min) + 10 ns)
tRFC(2 Gb) = 160 ns
All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron
MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD).
Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns
and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins:
tMRD(min) = 4 nCK
tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK
at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
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This build is stripped down. It boots to the command prompt.
GPIO is the only peripheral supported. Others TBD.
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This patch adds basic Tegra114 (T114) build support - no specific
board is targeted.
Signed-off-by: Tom Warren <twarren@nvidia.com>
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These are stripped down for bringup, They'll be filled out later
to match-up with the kernel DT contents, and/or as devices are
brought up (mmc, usb, spi, etc.).
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Add driver for tegra SPI "SLINK" style driver. This controller is
similar to the tegra20 SPI "SFLASH" controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Add tegra30 SPI SLINK nodes to fdt.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Add node for tegra20 SPI SFLASH controller to fdt.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Add back host1x node to seaboard dts file. This got dropped during
the tegra fdt sort.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The libfdt.h file is the definition file for libfdt. It is unnecessary
to include other fdt header files (the necessary ones are pulled in
by libfdt.h).
Signed-off-by: Gerald Van Baren <gvb@unssw.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
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This mux is not currently used and appears to be a carry-over from the
am335x evm code.
Acked-by: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
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