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2017-04-25Merge git://git.denx.de/u-boot-sunxiTom Rini
2017-04-25Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-04-25arm: socfpga: add cyclone5 based de10-nano boardDalon Westergreen
Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-24armv8: layerscape: Fix DDR size calcuation for SPL buildYork Sun
Commit 088454cd dropped return value from initram(), setting gd->ram_size directly. Three boards were missed for SPL boot. Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: ls1046aqds: Integrate FSL PPAHou Zhiqiang
The PPA is a EL3 firmware, which support PSCI, hotplug, power-management features etc. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: ls1043aqds: Integrate FSL PPAHou Zhiqiang
The PPA is a EL3 firmware, which support PSCI, hotplug, power-management features etc. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: ls2080ardb: Add phy number for serdes1 protocol 0x4bSantan Kumar
Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033Alison Wang
Since commit ce412b7, RGMII TX clock internal delay is not enabled for AR8033 unconditionally. On LS1021ATWR board, the third port eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to be enabled. This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX clock internal delay for AR8033 on the third port. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-21sunxi: add support for Lichee Pi ZeroIcenowy Zheng
Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-21sunxi: add basic V3s supportIcenowy Zheng
Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add clock support for DE2/HDMI/TCON on newer SoCsJernej Skrabec
This is needed for HDMI, which will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add support for Bananapi M2 UltraChen-Yu Tsai
The Bananapi M2 Ultra is the first publicly available development board featuring the R40 SoC. This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra, as well as a defconfig for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add PSCI support for R40Chen-Yu Tsai
The R40's CPU controls are a combination of sun6i and sun7i. All controls are in the CPUCFG block, and it seems the R40 does not have a PRCM block. The core reset, power gating and clamp controls are grouped like sun6i. Last, the R40 does not have a secure SRAM block. This patch adds a PSCI implementation for CPU bring-up and hotplug for the R40. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Enable SPL for R40Chen-Yu Tsai
Now that we can do DRAM initialization for the R40, we can enable SPL support for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Provide defaults for R40 DRAM settingsChen-Yu Tsai
These values were taken from the Banana Pi M2 Ultra fex file found in the released vendor BSP. This is the only publicly available R40 device at the time of this writing. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add mmc[1-3] pinmux settings for R40Chen-Yu Tsai
The PIO is generally compatible with the A20, except that it routes the full 8 bits and eMMC reset pins for mmc2. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Enable AXP221s in I2C mode with the R40 SoCChen-Yu Tsai
The R40 SoC uses the AXP221s in I2C mode to supply power. Some regulator's common usages have changed, and also the recommended voltage for existing usages have changed. Update the defaults to match. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add initial support for R40Chen-Yu Tsai
The R40 is the successor to the A20. It is a hybrid of the A20, A33 and the H3. The R40's PIO controller is compatible with the A20, Reuse the A20 UART and I2C muxing code by adding the R40's macro. The display pipeline is the newer DE 2.0 variant. Block enabling video on R40 for now. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Split up long Kconfig linesChen-Yu Tsai
Currently we have some lines in board/sunxi/Kconfig that are very long. These line either provide default values for a set of SoCs, or limit some option to a subset of sunxi SoCs. Fortunately Kconfig makes it easy to split them. The Kconfig language document states If multiple dependencies are defined, they are connected with '&&'. This means we can split existing dependencies at "&&" symbols. This applies to both the "depends on" lines and "if" expressions. This patch splits them up to one symbol per line. This will make it easier to add, remove, or modify one item at a time. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Convert CONFIG_MACPWR to KconfigMylène Josserand
Convert the CONFIG_MACPWR to Kconfig and update all the sunxi defconfigs that used it in SYS_EXTRA_OPTIONS. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Convert CONFIG_SATAPWR to KconfigMylène Josserand
Convert the CONFIG_SATAPWR into kconfig. Thanks to that, many SYS_EXTRA_OPTIONS can be removed from some defconfigs. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-18Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-04-18board: Remove orphan SPARC boardsTom Rini
Since 936478e797a8 SPARC as been removed as an architecture. Remove these now orphan boards. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-18blackfin: ibf-dsp561: remove orphan Blackfin boardMasahiro Yamada
This is a Blackfin board that commit ea3310e8aafa ("Blackfin: Remove") missed to remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-18sunxi: Add maintainer of the NanoPi NEO AirJelle van der Waa
Add myself as maintainer of the NanoPi NEO Air board. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-17powerpc/board/t1024rdb: enable board-level reset when issuing reset commandShengzhou Liu
As board-specific reset logic, it needs to issue reset signal via CPLD when issuing 'reset' command in u-boot, this patch solves the issue of reset command not working on T1024RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv7: ls1021a: Drop macro CONFIG_LS102XAYork Sun
Use CONFIG_ARCH_LS1021A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17arm: ls1046ardb: Add SD secure boot targetRuchika Gupta
- Add SD secure boot target for ls1046ardb. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM (128K) where 32K are reserved for use by boot ROM and 6K for the header. - Reduce the size of CAAM driver for SPL Blobification functions and descriptors, that are not required at the time of SPL are disabled. Further error code conversion to strings is disabled for SPL build. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17arm: ls1043ardb: Add NAND secure boot targetRuchika Gupta
Add NAND secure boot target for ls1043ardb. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript from NAND to DDR. Offsets for Bootscript on NAND and DDR have been also defined. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17arm: ls1043ardb: Add SD secure boot targetRuchika Gupta
- Add SD secure boot target for ls1043ardb. - Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM (128K) where 32K are reserved for use by boot ROM and 6K for secure boto header. - Error messages during SPL boot are limited to error code numbers instead of strings to reduce the size of SPL image. Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: LS1012ARDB: Add QSPI Secure Boot targetVinitha Pillai-B57223
Add QSPI Secure Boot target to enable chain of trust Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: LS1046ARDB: Add QSPI Secure Boot targetVinitha Pillai-B57223
Add QSPI Secure Boot target. Also enable sec init. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: LS1046AQDS: Add NOR Secure Boot TargetSumit Garg
Add NOR secure boot target. Also enable sec init. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls1046ardb: SPL size reductionSumit Garg
Using changes in this patch we were able to reduce approx 4k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size: 1. Changes in board/freescale/ls1046ardb/Makefile to remove compilation of eth.c and cpld.c in case of SPL build. 2. Changes in board/freescale/ls1046ardb/ls1046ardb.c to keep only ddr_init and board_early_init_f funcations in case of SPL build. 3. Changes in ls1046a_common.h & ls1046ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build. 4. Disable MMC driver from bieng compiled in case of SPL NAND build and NAND driver from bieng compiled in case of SPL MMC build. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls1043ardb: SPL size reductionSumit Garg
Using changes in this patch we were able to reduce approx 10k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size: 1. Changes in board/freescale/ls1043ardb/Makefile to remove compilation of eth.c and cpld.c in case of SPL build. 2. Changes in board/freescale/ls1043ardb/ls1043ardb.c to keep only ddr_init and board_early_init_f funcations in case of SPL build. 3. Changes in ls1043a_common.h & ls1043ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build. 4. Disable MMC driver from bieng compiled in case of SPL NAND build and NAND driver from bieng compiled in case of SPL MMC build. 5. Remove I2C driver support from SPL in case of LS1043ARDB. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-16Merge git://git.denx.de/u-boot-rockchipTom Rini
2017-04-16Merge git://git.denx.de/u-boot-dmTom Rini
2017-04-15rockchip: ARM64: split RK3399-Q7 board off the RK3399-EVB boardKlaus Goger
The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3399. It provides the following feature set: * up to 4GB DDR3 * on-module SPI-NOR flash * on-module eMMC (with 8-bit interace) * SD card (on a baseboad) via edge connector * Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY * HDMI/eDP/MIPI displays * 2x MIPI-CSI * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub) * on-module STM32 Cortex-M0 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) - USB<->CAN bridge controller Note that we use a multi-payload FIT image for booting and have Cortex-M0 payload in a separate subimage: we thus rely on the FIT image loader to put it into the SRAM region that ATF expects it in. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixed build warning on puma-rk3399: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-14board: sama5d3_xplained: Enable early debug UARTWenyou Yang
Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-04-14board: sama5d3_xplained: Clean up codeWenyou Yang
Due to the introduction of the pinctrl and clk driver, and using device tree files, remove the unneeded hardcoded pin configuration and clock enabling code from the board file. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-04-14board: sama5d3_xplained: Update to support DM/DTWenyou Yang
Update the configuration files to support the device tree and driver model, so do SPL. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Fix build error with sama5d3_xplained_mmc: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-14board: sama5d3xek: Enable early debug UARTWenyou Yang
Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-04-14board: sama5d3xek: Clean up codeWenyou Yang
Due to the introduction of the pinctrl and clk driver, and using device tree files, remove the unneeded hardcoded pin configuration and clock enabling code from the board file. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Remove CONFIG_PHY_MICREL as per previous patch: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-14board: sama5d3xek: Update to support DM/DTWenyou Yang
Update the configuration files to support the device tree and driver model, so do SPL. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Add back CONFIG_PHY_MICREL to prevent a build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-14Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini
2017-04-14Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2017-04-14ARM: socfpga: Rename MCVEVKMarek Vasut
The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
2017-04-14board: toradex: colibri_vf: Add DCU support for Colibri VybridStefan Agner
The Vybrid SoC family has the same display controller unit (DCU) like the LS1021A SoC. This patch adds platform data, pinmux defines and clock control to enable the driver for Toradex Colibri Vybrid module. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-04-14Convert CONFIG_FSL_DCU_FB to KconfigSanchayan Maity
Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Alison Wang <alison.wang@nxp.com>
2017-04-13Merge git://git.denx.de/u-boot-dmTom Rini
Here with some DM changes as well as the long-standing AT91 DM/DT conversion patches which I have picked up via dm.