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path: root/configs/socfpga_vining_fpga_defconfig
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2016-09-09configs: Resync with savedefconfigTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-07Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROLMasahiro Yamada
If both SPL_DM and SPL_OF_CONTROL are enabled, SPL needs to bind several devices, but CONFIG_SYS_MALLOC_F_LEN=0x400 is apparently not enough. Increase the default to 0x2000 for the case. This will be helpful for shorter defconfigs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-09common: bootdelay: move CONFIG_BOOTDELAY into a Kconfig optionHeiko Schocher
move CONFIG_BOOTDELAY into a Kconfig option. Used for this purpose the moveconfig.py tool in tools. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2016-06-01arm: socfpga: Enable tiny printf and simple malloc in SPLMarek Vasut
Enable both features to reduce the SPL size by 6 kiB. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de>
2016-06-01arm: socfpga: Add samtec VIN|ING boardMarek Vasut
Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request