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path: root/cpu/arm926ejs/versatile/timer.c
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2008-08-25Correct ARM Versatile Timer InitializationGururaja Hebbar K R
- According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271), -- Timer Value Register @ TIMER Base + 4 is Read-only. -- Prescale Value (Bits 3-2 of TIMER Control register) can only be one of 00,01,10. 11 is undefined. -- CFG_HZ for Versatile board is set to #define CFG_HZ (1000000 / 256) So Prescale bits is set to indicate - 8 Stages of Prescale, Clock divided by 256 - The Timer Control Register has one Undefined/Shouldn't Use Bit So we should do read/modify/write Operation Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
2006-03-13Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific timer andWolfgang Denk
cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories Patch by Andreas Engel, 13 Mar 2006