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path: root/cpu/mpc85xx/cpu_init.c
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2008-06-10MPC85xx: Beautify boot output of L2 cache configurationWolfgang Grandegger
The boot output is now aligned poperly with other boot output lines, e.g.: FLASH: 128 MB L2: 512 KB enabled Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
2008-04-1185xx: Use SVR_SOC_VER instead of SVR_VERKumar Gala
The recent change introduced by 'Update SVR numbers to expand support' now requires that we use SVR_SOC_VER instead of SVR_VER if we want to compare against a particular processor id. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-2685xx: Added support for multicore boot mechanismKumar Gala
Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-2685xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala
When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-1785xx: Get ride of old TLB setup codeKumar Gala
Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-1785xx: Reworked initial processor initKumar Gala
Reworked the initial processor initialzation sequence: * introduced cpu_early_init_f that is run in address space 1 (AS=1) * Moved TLB/LAW and CCSR init into cpu_early_init_f() * Reworked initial asm code to do most of the core init before TLBs The main reasons for these changes are to allow handling of 36-bit phys addresses in the future and some of the issues that will exist when we do that. There are a few caveats on what can be initialized via the LAW and TLB static tables: * TLB entry 14/15 can't be initialized via the TLB table * any LAW that covers the implicit boot window (4G-8M to 4G) must map to the code that is currently executing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-1685xx: Move LAW init code into CKumar Gala
Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11Stop using immap_t on 85xxKumar Gala
In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11Stop using immap_t for cpm offset on 85xxKumar Gala
In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-08-29Enable L2 cache for MPC8568MDS boardHaiying Wang
The L2 cache size is 512KB for 8568, print out the correct informaiton. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2007-08-14Add support for UEC to 8568Andy Fleming
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-14Fix minor 85xx warningsAndy Fleming
Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-14mpc85xx L2 cache reporting and SRAM relocation option.Ed Swarthout
Allow debugger to override flash cs0/cs1 settings to enable alternate boot regions Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2007-05-02Add support for the 8568 MDS boardAndy Fleming
This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming <afleming@freescale.com>
2006-06-28* Add Flat Dev Tree construction for MPC85xx ADS and CDS boardsMatthew McClintock
Patch by Jon Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-03-31GCC-4.x fixes: clean up global data pointer initialization for all boards.Wolfgang Denk
2005-07-25* Patch by Jon Loeliger, 2005-05-05Jon Loeliger
Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
2005-07-25* Patch by Jon Loeliger 2005-02-08Jon Loeliger
Determine L2 Cache size dynamically on 85XX boards.
2005-07-23* Patch by Jon Loeliger, Kumar Gala 2005-02-08Jon Loeliger
- Convert the CPM2 based functionality to use new CONFIG_CPM2 option rather than a myriad of CONFIG_MPC8560-like variants. Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560. Eliminates the CONFIG_MPC8560 option entirely. Distributes the new CONFIG_CPM2 option to each 8260 board.
2005-03-15Update code for TQM8540 board (and 85xx in general):wdenk
- Change the name of the Ethernet driver: MOTO ENET -> ENET - Reformat boot messages - Enable redundant environment - Replace the -O2 optimization flag with -mno-string
2003-10-15* Patches by Xianghua Xiao, 15 Oct 2003:wdenk
- Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup
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