Age | Commit message (Collapse) | Author |
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Added memory, CPU, UART, I2C and SPR POST tests for PPC440.
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
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This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.
Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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The EBC Configuration Register is now by CFG_EBC_CFG definable
Added JFFS2 support for the SC3 board.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Some code cleanup.
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Signed-off-by: Heiko Schocher <hs@denx.de>
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This code will optimize the DDR2 controller setup on a board specific
basis.
Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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- Add configuration of Open Drain GPIO Output selection
- Add configuration of initial value of GPIO output pins
Patch by Tolunay Orkun, 07 Apr 2006
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Patch by Stefan Roese, 02 Jun 2006
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now handling all 4xx cpu's.
Patch by Stefan Roese, 16 Aug 2005
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Patch by Stefan Roese, 08 Aug 2005
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Patch by Steven Blakeslee, 27 Jul 2005
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(tschaefer@giga-stream.de). Now inital stack in data cache can be used even if the chip select is in use.
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PPC405GP designs.
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