Age | Commit message (Collapse) | Author | |
---|---|---|---|
2007-01-05 | [PATCH] Add DDR2 optimization code for Sequoia (440EPx) board | Stefan Roese | |
This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de> | |||
2006-11-27 | [PATCH] Update Prodrive ALPR board support (440GX) | Stefan Roese | |
Signed-off-by: Stefan Roese <sr@denx.de> | |||
2006-10-12 | * PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely. | Stefan Roese | |
- Add configuration of Open Drain GPIO Output selection - Add configuration of initial value of GPIO output pins Patch by Tolunay Orkun, 07 Apr 2006 | |||
2006-06-02 | Add support for PCS440EP board | Stefan Roese | |
Patch by Stefan Roese, 02 Jun 2006 | |||
2006-03-31 | GCC-4.x fixes: clean up global data pointer initialization for all boards. | Wolfgang Denk | |
2005-08-16 | Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c | Stefan Roese | |
now handling all 4xx cpu's. Patch by Stefan Roese, 16 Aug 2005 | |||
2005-08-08 | Changed CONFIG_440_xx to CONFIG_440xx for a consistent design (405 and linux) | Stefan Roese | |
Patch by Stefan Roese, 08 Aug 2005 | |||
2005-08-01 | Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. | Stefan Roese | |
Patch by Steven Blakeslee, 27 Jul 2005 | |||
2003-06-05 | - Fix bug for initial stack in data cache as pointed out by Thomas Schaefer ↵ | stroese | |
(tschaefer@giga-stream.de). Now inital stack in data cache can be used even if the chip select is in use. | |||
2003-05-23 | PPC405EP support added. | stroese | |
2003-04-04 | Changed PPC405GPr version from A to B. | stroese | |
2003-03-20 | Set edge conditioning circuitry on PPC405GPr for compatibility to existing ↵ | stroese | |
PPC405GP designs. | |||
2002-08-27 | Initial revision | wdenk | |