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path: root/cpu/ppc4xx/denali_spd_ddr2.c
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2008-04-29ppc4xx: Fix compilation warning in denali_spd_ddr2.cStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-29ppc4xx: Complete remove bogus dflush()Stefan Roese
Since the current dflush() implementation is know to have some problems (as seem on lwmon5 ECC init) this patch removes it completely and replaces it by using clean_dcache_range(). Tested on Katmai with ECC DIMM. Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-31ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setupLarry Johnson
Signed-off-by: Larry Johnson <lrj@acm.org>
2008-02-14ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD codeLarry Johnson
Signed-off-by: Larry Johnson <lrj@acm.org>
2007-12-27Add 440EPx DDR2 SPD DIMM supportLarry Johnson
This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets. Signed-off-by: Larry Johnson <lrj@acm.org>