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2007-10-31ppc4xx: 4xx_pcie: Disable debug output as defaultStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support addedStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & KatmaiStefan Roese
128MB seems to be the smallest possible value for the memory size for on PCIe port. With this change now the BAR's of the PCIe cards are accessible under U-Boot. One big note: This only works for PCIe port 0 & 1. For port 2 this currently doesn't work, since the base address is now 0xc0000000 (0xb0000000 + 2 * 0x08000000), and this is already occupied by CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean to change the base addresses completely and this change would have too much impact right now. This patch adds debug output to the 4xx pcie driver too. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: 4xx_pcie: Fix problem with SDRN access using port number as idxStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platformsStefan Roese
These files were introduced with the IBM 405GP but are currently used on all 4xx PPC platforms. So the name doesn't match the content anymore. This patch renames the files to 4xx_pci.c/h. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Add a comment for 405EX PCIe endpoint configurationStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)Stefan Roese
(3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access the SDR registers of the PCIe ports. This makes the overall design clearer, since it removed a lot of switch statements which are not needed anymore. Also, the functions ppc4xx_init_pcie_rootport() and ppc4xx_init_pcie_entport() are merged into a single function ppc4xx_init_pcie_port(), since most of the code was duplicated. This makes maintainance and porting to other 4xx platforms easier. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)Stefan Roese
This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (2) This patch renames the functions from 440spe_ to 4xx_ with a little additional cleanup Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)Stefan Roese
This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-02ppc4xx: Coding style cleanupStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-02Program EPLD to force full duplex mode for PHY.Grzegorz Bernacki
EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-09-07[PPC440SPe] Improve PCIe configuration space accessGrzegorz Bernacki
- correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-09-07[PPC440SPe] Convert machine check exceptions handlingGrzegorz Bernacki
Convert using fixup mechanism to suppressing MCK for the duration of config read/write transaction: while fixups work fine with the case of a precise exception, we identified a major drawback with this approach when there's an imprecise case. In this scenario there is the following race condition: the fixup is (by design) set to catch the instruction following the one actually causing the exception; if an interrupt (e.g. decrementer) happens between those two instructions, the ISR code is executed before the fixup handler the machine check is no longer protected by the fixup handler as it appears as within the ISR code. In consequence the fixup approach is being phased out and replaced with explicit suppressing of MCK during a PCIe config read/write cycle. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-08-18lib_ppc: make board_add_ram_info weakKim Phillips
platforms wishing to display RAM diagnostics in addition to size, can do so, on one line, in their own board_add_ram_info() implementation. this consequently eliminates CONFIG_ADD_RAM_INFO. Thanks to Stefan for the hint. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-14Merge with git://www.denx.de/git/u-boot.gitStefan Roese
2007-08-14Coding style cleanupStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-14Merge with /home/stefan/git/u-boot/zeusStefan Roese
2007-08-14ppc4xx: Add initial Zeus (PPC405EP) board supportStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-13ppc4xx: Fix problem in PLL clock calculationStefan Roese
This patch was originall provided by David Mitchell <dmitchell@amcc.com> and fixes a bug in the PLL clock calculation. Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-07Merge with git://www.denx.de/git/u-boot.gitMarkus Klotzbuecher
2007-08-06Merge with /home/wd/git/u-boot/custodian/u-boot-testingWolfgang Denk
2007-08-06Coding style cleanup. Update CHANGELOG.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-08-03Merge branch 'testing' into workingAndy Fleming
Conflicts: CHANGELOG fs/fat/fat.c include/configs/MPC8560ADS.h include/configs/pcs440ep.h net/eth.c
2007-08-02ppc4xx: Code cleanupStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-02[ppc440SPe] Graceful recovery from machine check during PCIe configurationGrzegorz Bernacki
During config transactions on the PCIe bus an attempt to scan for a non-existent device can lead to a machine check exception with certain peripheral devices. In order to avoid crashing in such scenarios the instrumented versions of the config cycle read routines are introduced, so the exceptions fixups framework can gracefully recover. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Rafal Jaworowski <raj@semihalf.com>
2007-08-02[ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.ARafal Jaworowski
This brings back separate settings for PCIe bus numbers depending on chip revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa commit. 440SPe rev. A does NOT work properly with the same settings as for the rev. B (no devices are seen on the bus during enumeration). Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2007-07-31ppc4xx: Update AMCC Bamboo 440EP supportEugene OBrien
Changed storage type of cfg_simulate_spd_eeprom to const Changed storage type of gpio_tab to stack storage (Cannot access global data declarations in .bss until afer code relocation) Improved SDRAM tests to catch problems where data is not uniquely addressable (e.g. incorrectly programmed SDRAM row or columns) Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules Fixed AM29LV320DT (OpCode Flash) sector map Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-30ppc4xx: Only print ECC related info when the error bis are setStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-26ppc4xx: Add support for AMCC 405EP Taihu boardJohn Otken
Signed-off-by: John Otken <john@softadvances.com>
2007-07-20ppc4xx: Fix bug with default GPIO output valueStefan Roese
As spotted by Matthias Fuchs, the default output values for all GPIO1 outputs were not setup correctly. This patch fixes this issue. Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16Merge with git://www.denx.de/git/u-boot.gitStefan Roese
2007-07-16ppc4xx: Code cleanupStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16ppc4xx: Add new weak functions to support boardspecific DDR2 configurationStefan Roese
The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better support non default, boardspecific DDR(2) controller configuration. Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16ppc4xx: Add remove_tlb() function to remove a mem area from TLB setupStefan Roese
The new function remove_tlb() can be used to remove the TLB's used to map a specific memory region. This is especially useful for the DDR(2) setup routines which configure the SDRAM area temporarily as a cached area (for speedup on auto-calibration and ECC generation) and later need this area uncached for normal usage. Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-12ppc4xx: Change receive buffer handling in the 4xx emac driverStefan Roese
This change fixes a bug in the receive buffer handling, that could lead to problems upon high network traffic (broadcasts...). Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-12Update CHANGELOG, minor coding style cleanup.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-07-10cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols.Jon Loeliger
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-09cpu/[7a-ln-z]*: Remove obsolete references to CONFIG_COMMANDSJon Loeliger
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-10Coding style cleanup; update CHANGELOG.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-07-09Merge with /home/hs/Atronic/u-bootWolfgang Denk
2007-07-06Fix problem with get/setdcr commands introduced by cfg patchesStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-05Merged POST framework with the current TOT.Sergei Poselenov
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2007-07-04Fix a few file permission problems.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-07-04cpu/ non-mpc*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*).Jon Loeliger
This is a compatibility step that allows both the older form and the new form to co-exist for a while until the older can be removed entirely. All transformations are of the form: Before: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) After: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-06-25Merge with git://www.denx.de/git/u-boot.gitStefan Roese
2007-06-25[PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANGHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de>
2007-06-25ppc4xx: PPC440EPx Emit DDR0 registers on machine check interruptNiklaus Giger
This patch prints the DDR status registers upon machine check interrupt on the 440EPx/GRx. This can be useful especially when ECC support is enabled. I added some small changes to the original patch from Niklaus to make it compile clean. Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com> Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-25ppc4xx: Fix O=buildir buildsNiklaus Giger
This patch fixes the problem to assemble cpu/ppc4xx/start.S experienced last week where building failed having specified O=../build.sequoia. Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
2007-06-25ppc4xx: Add pci_pre_init() for 405 boardsMatthias Fuchs
This patch adds support for calling a plattform dependant pci_pre_init() function for 405 boards. This can be used to move the current pci_405gp_fixup_irq() function into the board code. This patch also makes the CFG_PCI_PRE_INIT define obsolete. A default function with 'weak' attribute is used when a board specific pci_pre_init() is not implemented. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-06-22Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk
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