Age | Commit message (Collapse) | Author |
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buffer pointers
Block device read/write is anonymous data; there is no need to use a
typed pointer. void * is fine. Also add a hook for block_read functions
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Each of the filesystem drivers duplicate the get_dev routine. This change
merges them into a single function in part.c
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Previously the strapping DCR/SDR was read to determine if the internal PCI
arbiter is enabled or not. This strapping bit can be overridden, so now
the current status is read from the correct DCR/SDR register.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Identification Register (CIR).
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The EBC Configuration Register is now by CFG_EBC_CFG definable
Added JFFS2 support for the SC3 board.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Some code cleanup.
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Signed-off-by: Stefan Roese <sr@denx.de>
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Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Heiko Schocher <hs@denx.de>
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This patch fixes a problem with an incorrect setup for the refresh
timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c
Signed-off-by: Stefan Roese <sr@denx.de>
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This code will optimize the DDR2 controller setup on a board specific
basis.
Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Heiko Schocher <hs@denx.de>
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Signed-off-by: Heiko Schocher <hs@denx.de>
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The soc node of the mpc52xx needs to be loaded with the IPB bus frequency,
not the XLB frequency.
This patch depends on the previous patches for MPC52xx device tree support
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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This patch adds support for the Prodrive P3M750 (PPC750 & MV64460)
and the P3M7448 (MPC7448 & MV64460) PMC modules. Both modules are
quite similar and share the same board directory "prodrive/p3mx"
and the same config file "p3mx.h".
Signed-off-by: Stefan Roese <sr@denx.de>
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Implement various code style fixes and similar changes.
Signed-off-by: Timur Tabi <timur@freescale.com>
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This patch adds the code and configuration necessary to boot with an
arch/powerpc Linux kernel.
Signed-off-by: Grant Likely <grant.likely@gmail.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Patch below corrects the setting of the zmiifer register, it was
overwritting the register rather than ORing the settings.
Signed-off-by: Neil Wilson <NWilson@airspan.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Fixed cpu/ppc4xx/start.S for 440EPx Errata: further corrects PPC440EPx
errata 1.12: 440_33 by moving patch up in code.
Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
Added multiple I2C bus support to fsl_i2c.c.
Signed-off-by: Timur Tabi <timur@freescale.com>
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Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.
Signed-off-by: Timur Tabi <timur@freescale.com>
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The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Update 83xx OF code to update local-mac-address properties
for ethernet instead of the obsolete 'address' property.
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MPC8360EMDS
This patch also adds an improved I2C set_speed(), which handles all clock
frequencies.
Signed-off-by: Timur Tabi <timur@freescale.com>
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this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
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