Age | Commit message (Collapse) | Author | |
---|---|---|---|
2018-03-19 | ram: stm32mp1: add driver | Patrick Delaunay | |
Add driver and binding for stm32mp1 ddr controller and phy Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> | |||
2017-07-26 | ram: stm32: add second SDRAM bank management | Patrice Chotard | |
FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank. Even if only bank2 is used, some bank1 registers must be configured. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> | |||
2017-05-08 | ARM: DT: stm32f7: add sdram pin contol node | Vikas Manocha | |
Also added DT binding doc for stm32 fmc(flexible memory controller). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |