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2018-09-22pinctrl: bcm6838: add pinctrl supportPhilippe Reynes
Add pinctrl support for broadcom bcm6838 SoC. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-09-11remoteproc: Introduce K3 remoteproc driverLokesh Vutla
Add support for K3 based remoteproc driver that communicates with TISCI to start start a remote processor. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11remoteproc: Introduce K3 system controllerLokesh Vutla
K3 specific SoCs have a dedicated microcontroller for doing resource management. Any HLOS/firmware on compute clusters should load a firmware to this microcontroller before accessing any resource. Adding support for loading this firmware. After the K3 system controller got loaded with firmware and started up it sends out a boot notification message through the secure proxy facility using the TI SCI protocol. Intercept and receive this message through the rproc start operation which will need to get invoked explicitly after the firmware got loaded. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-11mailbox: Introduce K3 Secure Proxy DriverLokesh Vutla
Secure Proxy module manages hardware threads that are meant for communication between the processor entities. Adding support for this driver. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2018-09-11sysreset: Add TI System Control Interface (TI SCI) sysreset driverAndreas Dannenberg
Devices from the TI K3 family of SoCs like the AM654x contain a Device Management and Security Controller (SYSFW) that manages the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a system reset driver that communicates to the system controller over the TI SCI protocol for allowing to perform a system- wide SoC reset. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11power domain: Introduce TI System Control Interface (TI SCI) power domain driverAndreas Dannenberg
Some TI Keystone 2 and K3 family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and the Device Management and Security Controller on AM65x SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a power domain driver that communicates to the system controller over the TI SCI protocol for performing power management of various devices present on the SoC. Various power domain functionalities are achieved by the means of different TI SCI device operations provided by the TI SCI framework. This code is loosely based on the drivers/soc/ti/ti_sci_pm_domains.c driver of the Linux kernel. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11clk: Introduce TI System Control Interface (TI SCI) clock driverAndreas Dannenberg
Some TI Keystone 2 and K3 family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and the Device Management and Security Controller on AM65x SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a clock driver that communicates to the system controller over the TI SCI protocol for performing clock management of various devices present on the SoC. Various clock functionality is achieved by the means of different TI SCI device operations provided by the TI SCI framework. This code is loosely based on the drivers/clk/keystone/sci-clk.c driver of the Linux kernel. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11reset: Introduce TI System Control Interface (TI SCI) reset driverAndreas Dannenberg
Some TI Keystone 2 and K3 family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and the Device Management and Security Controller on AM65x SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a reset driver that communicates to the system controller over the TI SCI protocol for performing reset management of various devices present on the SoC. Various reset functionalities are achieved by the means of different TI SCI device operations provided by the TI SCI framework. This code is loosely based on the drivers/reset/reset-ti-sci.c driver of the Linux kernel. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11firmware: Add basic support for TI System Control Interface (TI SCI) protocolLokesh Vutla
Texas Instrument's System Control Interface (TI SCI) message protocol is used in Texas Instrument's System on Chip (SoC) such as those in the K3 family AM654 SoC to communicate between various compute processors with a central system controller entity. The TI SCI message protocol provides support for management of various hardware entities within the SoC. Add support driver to allow communication with system controller entity within the SoC using the mailbox client. This is mostly derived from the TI SCI driver in Linux located at drivers/firmware/ti_sci.c. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2018-08-19drivers: regulator: fixed: add u-boot, off-on-delay-usPeng Fan
Add u-boot,off-on-delay-us for fixed regulator. Depends on board design, the gpio regulator sometimes connects with a big capacitance. When need to off, then on the regulator, if there is no enough delay, the voltage does not drop to 0, so introduce this property to handle such case. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-03dt-bindings: Document STM32 ADC DT bindingsFabrice Gasnier
This patch adds documentation of device tree bindings for the STM32 ADC. It's based on linux-v4.18-rc* dt-bindings, at the time of writing: - Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-31CREG GPIO: add device tree bindingsEugeniy Paltsev
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-24doc: Move device tree bindings documentation to doc/device-tree-bindingsBreno Lima
Currently the U-Boot project contains 2 documentation directories: - doc/ - Documentation/ The Documentation directory only contains device tree bindings related content, so move the 3 files to doc/device-tree-bindings/. Signed-off-by: Breno Lima <breno.lima@nxp.com>
2018-07-21spl: document 'chosen/u-boot, spl-boot-device'Philipp Tomsich
To let the full U-Boot know where it was booted from (i.e. which of the entries in /chosen/u-boot,spl-boot-order' contained a valid image), we define (and document) /chosen/u-boot,spl-boot-device as the property that could/should automatically be injected by SPL. This commit only contains a documentation change, which documents the new property and the intended usage. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-07-20stm32mp1: clk: support digital bypassPatrick Delaunay
HSE and LSE bypass shall support both analog and digital signals. This patch add a way to select digital bypas case in the device tree and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register during clock tree initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-09fdt: Add device tree memory bindingsMichael Pratt
Support a default memory bank, specified in reg, as well as board-specific memory banks in subtree board-id nodes. This allows memory information to be provided in the device tree, rather than hard-coded in, which will make it simpler to handle similar devices with different memory banks, as the board-id values or masks can be used to match devices. Signed-off-by: Michael Pratt <mpratt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2018-06-13x86: irq: Support discrete PIRQ routing registers via device treeBin Meng
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume consecutive PIRQ routing control registers. But this is not always the case on some platforms. Introduce a new device tree property intel,pirq-regmap to describe how the PIRQ routing register offset is mapped to the link number and adjust the irq router driver to utilize the mapping. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-04Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2018-05-29mvebu: pinctrl: sync compatible string with Linux 4.17-rc4Evan Wang
For pinctrl driver of mvebu, the compatible strings supported are defined differently from Linux version. The patch aligned the compatible string with Linux 4.17-rc4. Signed-off-by: Evan Wang <xswang@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-28device-tree-bindings: phy: Sync sun4i-usb-phy bindingsJagan Teki
Sync sun4i-usb-phy bindings from Linux, since the drivers/phy/allwinner/phy-sun4i-usb.c follow similar. Sync changes from Linux with below commit: "phy: sun4i-usb: add support for R40 USB PHY" (sha1: f3d96f8d23d8e6d0b7642ee946b9b2ac3418fb4d) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-25doc: device-tree-bindings: add Sandbox TPMv2.0 module infoMiquel Raynal
Add Sandbox TPMv2.0 module bindings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25doc: device-tree-bindings: add TIS TPMv2.0 SPI module infoMiquel Raynal
Add TIS TPMv2.0 SPI module bindings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-08power: regulator: Add support for stm32-vrefbufFabrice Gasnier
Add regulator driver for STM32 voltage reference buffer which can be used as voltage reference for ADCs, DACs and external components through dedicated VREF+ pin. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-04-11dm: i2c: dts: Add gpios and pinctrl device tree propertiesAlexander Kochetkov
The commit describe usage of gpios and pinctrl device tree properties in order to enable gpio-based software deblocking. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
2018-03-30doc: a37xx: Introduce pinctrl device tree bindingKen Ma
Reviewed-on: http://vgitil04.il.marvell.com:8080/43289 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-19clk: stm32mp1: add clock tree initializationPatrick Delaunay
add binding and code for clock tree initialization from device tree Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19ram: stm32mp1: add driverPatrick Delaunay
Add driver and binding for stm32mp1 ddr controller and phy Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-01-24dts: cadence_spi: Update documentation for DT bindingsJason Rush
Update documentation to reflect adopting the Linux DT bindings. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
2018-01-10doc: bindings: soft-spi: update documentation to match the codeMiquel Raynal
Linux bindings have been introduced in the code (removing the U-Boot specific ones) without documentation update. Compatible string has changed, as well as the four GPIO properties. Reflect this by updating the soft-spi.txt documentation. Fixes: 102412c415 ("dm: spi: soft_spi: switch to use linux compatible string") Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2017-12-12power: extend prefix match to regulator-name propertyFelix Brack
This patch extends pmic_bind_children prefix matching. In addition to the node name the property regulator-name is used while trying to match prefixes. This allows assigning different drivers to regulator nodes named regulator@1 and regulator@10 for example. I have discarded the idea of using other properties then regulator-name as I do not see any benefit in using property compatible or even regulator-compatible. Of course I am open to change this if there are good reasons to do so. Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-12-11ARC: clk: introduce HSDK CGU clock driverEugeniy Paltsev
Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-11-30rockchip: rk3399-puma: add code to allow forcing a power-on resetPhilipp Tomsich
The reset circuitry in the RK3399 only resets 'almost all logic' when a software reset is performed. To make our software maintenance easier in the future, we want to have the option (controlled by a DTS property) to force all reset causes other than a power-on reset to trigger a power-on reset via a GPIO trigger. This adds the necessary support to the rk3399-puma (i.e. RK3399-Q7) board-support and the documentation for the new property (sysreset-gpio) within the /config-node. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30dt-bindings: spi: Add andestech atcspi200 spi binding docRick Chen
Add a document to describe Andestech atcspi200 spi and binding information. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30dt-bindings: timer: Add andestech atcpit100 timerRick Chen
Add a document to describe Andestech atcpit100 timer and binding information. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-26ARM: socfpga: add bindings doc for arria10 fpga managerTien Fong Chee
This DT binding doc is porting from Linux DT binding doc. commit 1adcbea4201a6852362aa5ece573f1f169b28113 Add a device tree bindings document for the SoCFPGA Arria10 FPGA Manager driver. Signed-off-by: Alan Tull <atull@opensource.altera.com> Acked-by: Rob Herring <robh@kernel.org> Acked-By: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2017-11-21thermal: ti-bandgap: Add support for temperature sensorFaiz Abbas
The dra7xx series of SOCs contain a temperature sensor and an associated analog-to-digital converter (ADC) which produces an output which is proportional to the SOC temperature. Add support for this temperature sensor. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-17env: Save environment at the end of an MMC partitionJorge Ramirez-Ortiz
Allow the platform to define a partition by name at the end of which the environment data will be located. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-10-06doc: Fix statements on case sensitivity for regulator prefixFelix Brack
The regulator bindings state that regulator prefixes are allowd to be in upper or lower case. However pmic_bind_children from pmic_uclass uses strncmp to compare DT node name against prefix. This comparison is case sensitive hence the regulator driver prefix case matters. Signed-off-by: Felix Brack <fb@ltec.ch>
2017-10-01rockchip: spl: support a 'same-as-spl'-specifier in the spl-boot-orderPhilipp Tomsich
It is often desirable to configure the spl-boot-order (i.e. the order that SPL probes devices to find the FIT image containing a full U-Boot) such that it contains 'the same device the SPL stage was booted from' early on. To support this, we introduce the 'same-as-spl' specifier for the spl-boot-order property. This commit adds: - documentation for the new board_spl_was_booted_from() function that individual SoCs/boards should provide, if they can determine where the SPL was booted from - implements the new board_spl_was_booted_from() stub function - adds support for handling the 'same-as-spl' specifier and calling into the per-SoC/per-board support code. This also updates the documentation for the 'u-boot,spl-boot-order' property. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22dm: reset: add stm32 reset driverPatrice Chotard
This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22dm: clk: add clk driver support for stm32h7 SoCsPatrice Chotard
This driver implements basic clock setup, only clock gating is implemented. This driver doesn't implement .of_match as it's binded by MFD RCC driver. Files include/dt-bindings/clock/stm32h7-clks.h and doc/device-tree-bindings/clock/st,stm32h7-rcc.txt will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22usb: dwc3: Add dwc3 glue driver support for STiPatrice Chotard
This patch adds the ST glue logic to manage the DWC3 HC on STiH407 SoC family. It configures the internal glue logic and syscfg registers. Part of this code been extracted from kernel.org driver (drivers/usb/dwc3/dwc3-st.c) Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22usb: phy: Add STi USB2 PHYPatrice Chotard
This is the generic phy driver for the picoPHY ports used by USB2/1.1 controllers. It is found on STiH407 SoC family from STMicroelectronics. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-23i2c: add i2c driver for stm32Patrice Chotard
Add i2c driver which can be used on both STM32F7 and STM32H7. This I2C block supports the following features: _ Slave and master modes _ Multimaster capability _ Standard-mode (up to 100 kHz) _ Fast-mode (up to 400 kHz) _ Fast-mode Plus (up to 1 MHz) _ 7-bit and 10-bit addressing mode _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) _ All 7-bit addresses acknowledge mode _ General call _ Programmable setup and hold times _ Easy to use event management _ Optional clock stretching _ Software reset Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: add DRAM controller driver with DRAM initialisationPhilipp Tomsich
This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26ram: stm32: add second SDRAM bank managementPatrice Chotard
FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank. Even if only bank2 is used, some bank1 registers must be configured. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integerBin Meng
At present lpe/lpss-sio/scc FSP properties are all boolean, but in fact for "enable-lpe" it has 3 possible options. This adds macros for these options and change the property from a boolean type to an integer type, and change their names to explicitly indicate what the property is really for. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05x86: baytrail: Use macros instead of magic numbers for FSP settingsBin Meng
Introduce various meaningful macros for FSP settings and switch over to use them instead of magic numbers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05x86: baytrail: Remove "serial-debug-port-*" settingsBin Meng
"serial-debug-port-address" and "serial-debug-port-type" settings are actually reserved in the FSP UPD data structure. Remove them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-29doc: document u-boot, mmc-env-offset and u-boot, mmc-env-offset-redundPhilipp Tomsich
Adding documentation on the new config properties: 'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET 'u-boot,mmc-env-offset-redundant' - overrides CONFIG_ENV_OFFSET_REDUND Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>