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This version is based on the Marvell U-Boot version with this patch
applied as latest patch:
Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb
device mode" from 2016-07-05.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Hua Jing <jinghua@marvell.com>
Cc: Terry Zhou <bjzhou@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
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At present TPL uses the same options as SPL support. In a few cases the board
config enables or disables the SPL options depending on whether
CONFIG_TPL_BUILD is defined.
With the move to Kconfig, options are determined for the whole build and
(without a hack like an #undef in a header file) cannot be controlled in this
way.
Create new TPL options for these and update users. This will allow Kconfig
conversion to proceed for these boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Create drivers/sysreset and move sysreset-uclass and all sysreset
drivers there.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Booting a payload out of NAND FLASH from the SPL is a crux today, as
it requires hard partioned FLASH. Not a brilliant idea with the
reliability of todays NAND FLASH chips.
The upstream UBI + UBI fastmap implementation which is about to
brought to u-boot is too heavy weight for SPLs as it provides way more
functionality than needed for a SPL and does not even fit into the
restricted SPL areas which are loaded from the SoC boot ROM.
So this provides a fast and lightweight implementation of UBI scanning
and UBI fastmap attach. The scan and logical to physical block mapping
code is developed from scratch, while the fastmap implementation is
lifted from the linux kernel source and stripped down to fit the SPL
needs.
The text foot print on the board which I used for development is:
6854 0 0 6854 1abd
drivers/mtd/ubispl/built-in.o
Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are
reserved for the SPL) takes:
In full scan mode: 1172ms
In fastmap mode: 95ms
The code requires quite some storage. The largest and unknown part of
it is the number of fastmap blocks to read. Therefor the data
structure is not put into the BSS. The code requires a pointer to free
memory handed in which is initialized by the UBI attach code itself.
See doc/README.ubispl for further information on how to use it.
This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi
There is no way to share the fastmap code, as UBISPL only utilizes the
slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap()
from the original kernel ubi fastmap implementation.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
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A reset controller is a hardware module that controls reset signals that
affect other hardware modules or chips.
This patch defines a standard API that connects reset clients (i.e. the
drivers for devices affected by reset signals) to drivers for reset
controllers/providers. Initially, DT is the only supported method for
connecting the two.
The DT binding specification (reset.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/reset/reset.txt.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This allows a board to configure verified boot within the SPL using
a FIT or FIT with external data. It also allows the SPL to perform
signature verification without needing relocation.
The board configuration will need to add the following feature defines:
CONFIG_SPL_CRYPTO_SUPPORT
CONFIG_SPL_HASH_SUPPORT
CONFIG_SPL_SHA256
In this example, SHA256 is the only selected hashing algorithm.
And the following booleans:
CONFIG_SPL=y
CONFIG_SPL_DM=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_FIT_SIGNATURE=y
Signed-off-by: Teddy Reed <teddy.reed@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Dannenberg <dannenberg@ti.com>
Acked-by: Sumit Garg <sumit.garg@nxp.com>
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A mailbox is a hardware mechanism for transferring small message and/or
notifications between the CPU on which U-Boot runs and some other device
such as an auxilliary CPU running firmware or a hardware module.
This patch defines a standard API that connects mailbox clients to mailbox
providers (drivers). Initially, DT is the only supported method for
connecting the two.
The DT binding specification (mailbox.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Bring this in for SPL so that we can use generic code for loading from
block devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This function is implemented by the legacy block functions now. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Qualcom processors use proprietary bus to talk with PMIC devices -
SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's
multi-master and has simple autodetection capabilities.
This commit adds simple uclass that provides bus read/write interface.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).
Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.
We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Until now, the SoC selection for the ARCH_MVEBU platforms has been done
in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As
it needed to get selected for AXP and A38x based boards. This patch
now changes this to move the SoC selection to Kconfig. And also
uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x.
This makes things a bit clearer - especially for new board additions.
Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and
CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available
CONFIG_ARMADA_38X and CONFIG_ARMADA_XP.
And CONFIG_DDR3 is removed, as its not referenced anywhere.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one. This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.
Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
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This commit adds:
- new uclass id: UCLASS_ADC
- new uclass driver: drivers/adc/adc-uclass.c
The new uclass's API allows for ADC operation on:
* single-channel with channel selection by a number
* multti-channel with channel selection by bit mask
ADC uclass's functions:
* single-channel:
- adc_start_channel() - start channel conversion
- adc_channel_data() - get conversion data
- adc_channel_single_shot() - start/get conversion data
* multi-channel:
- adc_start_channels() - start selected channels conversion
- adc_channels_data() - get conversion data
- adc_channels_single_shot() - start/get conversion data for channels
selected by bit mask
* general:
- adc_stop() - stop the conversion
- adc_vdd_value() - positive reference Voltage value with polarity [uV]
- adc_vss_value() - negative reference Voltage value with polarity [uV]
- adc_data_mask() - conversion data bit mask
The device tree can provide below constraints/properties:
- vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1)
- vss-polarity-negative: if true: Vss = vss-microvolts * (-1)
- vdd-supply: phandle to Vdd regulator's node
- vss-supply: phandle to Vss regulator's node
And optional, checked only if the above corresponding, doesn't exist:
- vdd-microvolts: positive reference Voltage [uV]
- vss-microvolts: negative reference Voltage [uV]
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Implement a Timer uclass to work with lib/time.c.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
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Many System on Chip(SoC) solutions are complex with multiple processors
on the same die dedicated to either general purpose of specialized
functions. Many examples do exist in today's SoCs from various vendors.
Typical examples are micro controllers such as an ARM M3/M0 doing a
offload of specific function such as event integration or power
management or controlling camera etc.
Traditionally, the responsibility of loading up such a processor with a
firmware and communication has been with a High Level Operating
System(HLOS) such as Linux. However, there exists classes of products
where Linux would need to expect services from such a processor or the
delay of Linux and operating system being able to load up such a
firmware is unacceptable.
To address these needs, we need some minimal capability to load such a
system and ensure it is started prior to an Operating System(Linux or
any other) is started up.
NOTE: This is NOT meant to be a solve-all solution, instead, it tries to
address certain class of SoCs and products that need such a solution.
A very simple model is introduced here as part of the initial support
that supports microcontrollers with internal memory (no MMU, no
execution from external memory, or specific image format needs). This
basic framework can then (hopefully) be extensible to other complex SoC
processor support as need be.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.
This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.
This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print. Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.
We are often limited on code size for SPL. Besides, we still have
many boards that do not support device tree configuration. The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards. So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc. They must be
done in each low-level driver. In return, you can save much memory
footprint and it might be useful especially for SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Just preparing for upcoming cleaning.
The board-specific linker script board/vpac270/u-boot-spl.lds
has been touched to avoid build error. It does not change the
size of spl/u-boot-spl.bin for this board, so it should be OK.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.
Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and Exynos. This is useful but it would be better to have a
common API that can be understood and used throughout U-Boot.
Add a simple clock API as a starting point. It supports querying and setting
the rate of a clock. Each clock is a device. To reduce memory and processing
overhead the concept of peripheral clocks is provided. These do not need to
be explicit devices - it is possible to write a driver that can adjust the
I2C clock (for example) without an explicit I2C clock device. This can
dramatically reduce the number of devices (and associated overhead) in a
complex SoC.
Clocks are referenced by a number, and it is expected that SoCs will define
that numbering themselves via an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add support for a driver which sets up DRAM and can return information about
the amount of RAM available. This is a first step towards moving RAM init
to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a simple uclass for LEDs, so that these can be controlled by the device
tree and activated when needed. LEDs are referred to by their label.
This implementation requires a driver for each type of LED (e.g GPIO, I2C).
Signed-off-by: Simon Glass <sjg@chromium.org>
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It is useful to be able to keep track of the available CPUs in a multi-CPU
system. This uclass is mostly intended for use with SMP systems.
The uclass provides methods for getting basic information about each CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Add a new thermal uclass for thermal sensor and implement the imx
thermal driver basing on this uclass.
Signed-off-by: Ye.Li <B37916@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
[York Sun: Fix compiling error caused by u_qe_init()]
Reviewed-by: York Sun <yorksun@freescale.com>
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This patch split the Keystone II SGMII SerDes related code from
Ethernet driver and create a separate SGMII SerDes driver.
The SerDes driver can be used by others keystone subsystems
like PCI, sRIO, so move it to driver/soc/keystone directory.
Add soc specific drivers directory like in the Linux kernel.
It is going to be used by keysotone soc specific drivers.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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[1] Move driver/core/, driver/input/ and drivers/input/ entries
from the top Makefile to drivers/Makefile
[2] Remove the conditional by CONFIG_DM in drivers/core/Makefile
because the whole drivers/core directory is already selected
by CONFIG_DM in the upper level
[3] Likewise for CONFIG_DM_DEMO in drivers/demo/Makefile
[4] Simplify common/Makefile - both CONFIG_DDR_SPD and
CONFIG_SPD_EEPROM are boolean macros so they can directly
select objects
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
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add basic support for the pwm modul found on imx6.
Pieces of this code are based on linux code from drivers/pwm/pwm-imx.c
Commit "cd3de83f1476 Linux 3.16-rc4"
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
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Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF
definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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- Descend into drivers/fpga/ only when CONFIG_FPGA=y
- Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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This commit moves some drivers subdirectory entry
from the toplevel Makefile to drivers/Makefile
using Kbuild descending feature.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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