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With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.
Simple uses of sprintf are also converted to use strcpy.
Signed-off-by: Ben Whitten <ben.whitten@gmail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Conflicts:
arch/arm/Kconfig
Signed-off-by: Tom Rini <trini@konsulko.com>
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Until now, the SoC selection for the ARCH_MVEBU platforms has been done
in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As
it needed to get selected for AXP and A38x based boards. This patch
now changes this to move the SoC selection to Kconfig. And also
uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x.
This makes things a bit clearer - especially for new board additions.
Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and
CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available
CONFIG_ARMADA_38X and CONFIG_ARMADA_XP.
And CONFIG_DDR3 is removed, as its not referenced anywhere.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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This patch adds a new SATA driver for the Marvell Kirkwood and Armada
370 / XP SoC's.
This driver supports the SATA controller of some Mavell SoC's.
Here a (most likely incomplete) list of the supported SoC's:
- Kirkwood
- Armada 370
- Armada XP
This driver implementation is an alternative to the already available
driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
But this driver only supports PIO mode and as this new driver also
supports transfer via DMA, its much faster.
Please note, that the newer SoC's (e.g. Armada 38x) are not supported
by this driver. As they have an AHCI compatible SATA controller
integrated.
The original version of this driver was sent by Tor Krill to the U-Boot
list a few years ago. Here the link:
http://lists.denx.de/pipermail/u-boot/2010-June/073147.html
Changes by Stefan:
- Coding-style cleanup
- Support for Armada XP added
- MBUS window setup added
- D-cache flush and invalidation added - works with dcache enabled on
Armada XP
- Removed mdelay() from ata_wait_register() and add timer based timeout
detection to speed up the transfer
Signed-off-by: Tor Krill <tor@excito.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Tom Rini <trini@konsulko.com>
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This will allow the implementation to make use of data in the block_dev
structure beyond the base device number. This will be useful so that eMMC
block devices can encompass the HW partition ID rather than treating this
out-of-band. Equally, the existence of the priv field is crying out for
this patch to exist.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Convert this driver to use the new driver model PCI API.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Marek Vasut <marex@denx.de>
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Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
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The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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CONFIG_AHCI_SETFEATURES_XFER is not selected by any user, so delete
the dead code.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Now that we have a new header file for cache-aligned allocation, we should
move the stack-based allocation macro there also.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Tested-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This patch changes the initialization of the AHCI controller to not
enable the default interrupts (DEF_PORT_IRQ). As interrupts are
not used in U-Boot in general, this should not break the common AHCI
driver operation.
This change is needed to support the Marvell Armada 38x AHCI
controller. With interrupts enabled, this results in timeouts in
ahci_device_data_io(). Not enabling these interrupts fixes this
problem and the common AHCI driver works fine.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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When compling under 64bit platforms, there are lots of warnings,
like:
drivers/block/ahci.c:114:18: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
^
drivers/block/ahci.c: In function ?.hci_host_init?.
drivers/block/ahci.c:218:49: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
......
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
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The AHCI driver currently waits 5s before timing out when sending a
data command to a drive. Some drives take upwards of 8s to respond to
the initial data command while they're spinning up. Increase the
data io timeout to 10s so that those drives can be found on initial
scsi scan.
Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
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Enable full 48-bit LBA48 data reads by passing the upper word of the
LBA block pointer in bytes 9 and 10 of the FIS.
This allows uboot to load data from any arbitrary sector on a drive
with 2 or more TB of available data connected to an AHCI controller.
Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
[trini: Make use of CONFIG_SYS_64BIT_LBA in a few places to drop
warnings on platforms that don't enable that feature ]
Signed-off-by: Tom Rini <trini@konsulko.com>
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Function 'sprintf' does not check buffer boundaries but outputs
to the buffer of fixed size which could potentially cause buffer
overflow. Use a safer function to replace it.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
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Don't store it in a u32.
Don't dereference the bus address as if it were a virtual address
(fixes 284231e49a2b4 ("ahci: Support splitting of read transactions
into multiple chunks")).
Fixes crash on boot in MPC8641HPCN_36BIT target.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: York Sun <yorksun@freescale.com>
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In stead of user_buffer_size, transfer_size should be used to pass to
ahci_device_data_io(). transfer_size is the length that we want the
low level function to transfer each time.
If we use user_buffer_size which is the totally data length as parameter,
low level function will actually create many SGs to transfer as many data
as possible each time. That will produce many redundant data transfer.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Each time U-Boot boots on Intel Crown Bay board, the displayed hard
drive information is wrong. It could be either wrong capacity or just
a 'Capacity: not available' message. After enabling the debug switch,
we can see the scsi inquiry command did not execute successfully.
However, doing a 'scsi scan' in the U-Boot shell does not expose
this issue.
SCSI: Target spinup took 0 ms.
SATA link 1 timeout.
AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
ahci_device_data_io: 0 byte transferred. <--- scsi inquiry fails
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
Device 0: (0:0) Vendor: ATA Prod.: Rev: ?8
Type: Hard Disk
Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512)
Found 1 device(s).
So uninitialized contents on the stack were passed to dev_print() to
display those wrong information.
The symptom were observed on two hard drives (one is Seagate, the
other one is Western Digital). The fix is to make sure the AHCI
interface is not busy by checking the error and status information
from task file register after enabling the port in ahci_port_start()
before proceeding other operations like scsi_scan().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This allow the platform to handle a custom reset sequence.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
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Extract controller reset code from ahci_host_init() into separate
ahci_reset().
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
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The macro __iomem is defined in include/linux/compiler.h.
Let's include it rather than double __iomem defines.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
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- fix crash when sata device is not initialized
- remove disable_sata_clock() since it is not clear which clock for which
device should be disabled here
- call disable_sata_clock() for mx6 in preboot_os instead
Signed-off-by: Soeren Moch <smoch@web.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
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Add reset_sata() to the sata driver interface and implement it
for dwc_ahsata. This function cleans up after sata_init(), and
therefore accepts a device number like sata_init() does.
A dummy implementation is provided for the rest of the drivers.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
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Except the first loop, init_sata() should return 0 instead of 1
in the others.
This patch fix the issue of the 2nd sata port not workable on pci-sata card.
Signed-off-by: Pengbo Li <Pengbo.Li@freescale.com>
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U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
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The logic of the return statement in sata_port_status() calls for a
bitwise 'AND' operator, not logical 'AND'. Fix the typo.
Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
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This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
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The DMA/FIS buffers are set in ahci_port_start() which is called
after ahci_host_init(). So don't start the DMA engine here
(i.e. don't set FIS_RX)
This fixes the following error at kernel boot on OMAP platforms (e.g. DRA7x)
WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x260/0x358()
44000000.ocp:L3 Custom Error: MASTER SATA TARGET GPMC (Idle): Data Access in User mode during Functional access
Signed-off-by: Roger Quadros <rogerq@ti.com>
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This would be useful to start moving various config options.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
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This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.
The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.
The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port. This is added under a
suitable ifdef.
This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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In 73545f75b66d "ahci: wait longer for link" I increased the
timeout to 40ms based on the observed behaviour of a WD disk on a
Cubietruck. Since then Karsten Merker and myself have both
observed timeouts with HGST disks (Karsten on Cubietruck, me on
Cubieboard2). Increasing the timeout to ~175ms fixes this, so go
to 200ms for a bit of headroom.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Karsten Merker <merker@debian.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
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The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure
instead of attempting a memory access that results in a data abort and reset.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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Commit 2faf5fb82ed6 introduced a regression that causes a data
abort when running scsi init followed by scsi reset.
There are 2 problems with the original commit
1) ALLOC_CACHE_ALIGN_BUFFER() allocates memory on the stack but is
assigned to ataid[port] and used by other functions.
2) The function ata_scsiop_inquiry() tries to free memory which was
never allocated on the heap.
Fix these problems by using tmpid as a temporary cache aligned buffer.
Allocate memory separately for ataid[port] and re-use it if required.
Fixes: 2faf5fb82ed6 (ahci: Fix cache align error messages)
Reported-by: Eli Nidam <elini@marvell.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
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I have observed timeouts on a cubietruck.
The increase to 40ms is completely arbitrary and Works For Me(tm). I
couldn't find a good reference for how long you are supposed to wait,
although googling around it seems like tens of ms rather than single
digits is more common. I don't think there is any harm in waiting a bit
longer.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
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This allow the platform to register the platform ahci device.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
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With d6a320d we moved some clock externs out of blackfin_local.h and
into clock.h but now need to include <asm/clock.h> in more drivers to
avoid warnings.
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Tom Rini <trini@ti.com>
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Provide a way to use any host file or device as a block device in U-Boot.
This can be used to provide filesystem access within U-Boot to an ext2
image file on the host, for example.
The support is plumbed into the filesystem and partition interfaces.
We don't want to print a message in the driver every time we find a missing
device. Pass the information back to the caller where a message can be printed
if desired.
Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
- Removed change to part.c get_device_and_partition()
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Align the ATA ID buffer to the cache-line boundary. This gets rid
of the below error mesages on ARM v7 platforms.
scanning bus for devices...
ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818
CC: Aneesh V <aneesh@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
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If malloc() fails, we don't want to continue in ahci_init() and
ahci_init_one(). Also print a more informative error message on
malloc() failures.
CC: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
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Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Typoes fixed:
"partion" -> "partition"
"retrive", "retreive" -> "retrieve"
"th" -> "to"
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
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libata already has similar functions as implemented in the ahci code.
Refactor the code to use the libata variants and remove the dependency on
ata.h. Convert some defines to use the version from libata.h. Also, remove
some unnecessary memset's of bss data.
This is a step toward hopefully merging ahci.c and dw_ahsata.c which are
essentially the same driver.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Tom Rini <trini@ti.com>
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