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path: root/drivers/clk/clk_meson.c
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2018-11-20clk: meson: fix clk81 divider calculationJerome Brunet
clk81 divider is 0 based (meaning that 0 value in the register means divide by 1). Fix clk81 rate calculation for this. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-09-10clk: clk_meson: Add mux and div support for reparent and rate settingNeil Armstrong
This patch adds support for : - Rate calculation through muxes and generic dividers - Basic gate setting propagation - Reparenting for muxes - Clock rate setting through generic dividers without reparenting Support is only added to the Composite VPU and VAPB clocks in order to support the Video Processing Unit Power Domain clock setup. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-06-19clk: add Amlogic meson clock driverBeniamino Galvani
Introduce a basic clock driver for Amlogic Meson SoCs which supports enabling/disabling clock gates and getting their frequency. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>