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path: root/drivers/clk/clk_stm32mp1.c
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2018-07-20stm32mp1: clk: support digital bypassPatrick Delaunay
HSE and LSE bypass shall support both analog and digital signals. This patch add a way to select digital bypas case in the device tree and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register during clock tree initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20stm32mp1: clk: add ADC clock gatingPatrick Delaunay
Add ADC clock gating, that may be used by STM32 ADC. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20stm32mp1: clk: update Ethernet clock gatingPatrick Delaunay
Alignment with kernel clock driver Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20stm32mp1: clk: add LDTC and DSI clock supportPatrick Delaunay
This patch add clk_enable/clk_disable/clk_get_rate support for - DSI_PX - LTDC_PX - DSI_K (only get rate) These clocks are needed for LTDC and DSI drivers with latest device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20stm32mp1: clk: add common function pll_get_fvcoPatrick Delaunay
the function compute the VCO PLL freq, used in - stm32mp1_read_pll_freq() - pll_set_rate() Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> # Conflicts: # drivers/clk/clk_stm32mp1.c
2018-07-20stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macroPatrick Delaunay
This patch define RCC_PLLNCFGR2_SHIFT to reuse it in the pll function for set rate. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2018-07-20misc: stm32: Add STM32MP1 supportPatrick Delaunay
Following next kernel rcc bindings, we must use a MFD RCC driver which is able to bind both clock and reset drivers. We can reuse and adapt RCC MFD driver already available for MCU SoCs (F4/F7/H7). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-08clk: stm32mp1: Add VREF clock gatingFabrice Gasnier
Add VREF clock gating, that may be used by STM32 VREFBUF regulator. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-07SPDX: Convert all of our multiple license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-06clock: stm32mp1: add stgen clock source change supportPatrick Delaunay
The STGEN is the clock source for the Cortex A7 arch timer. So after modification of its frequency, CP15 cntfreq is updated and a new timer init is performed. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19clk: stm32mp1: add clock tree initializationPatrick Delaunay
add binding and code for clock tree initialization from device tree Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19clk: add driver for stm32mp1Patrick Delaunay
add RCC clock driver for STMP32MP157 - base on driver model = UCLASS_CLK - support ops to enable, disable and get rate of all SOC clock needed by U-Boot Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>