Age | Commit message (Collapse) | Author | |
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2019-04-23 | clk: mediatek: add support for SETCLR_INV and NO_SETCLR flags | Fabien Parent | |
Add the implementation for the CLK_GATE_SETCLR_INV and CLK_GATE_NO_SETCLR flags. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com> | |||
2018-11-28 | clk: MediaTek: add clock driver for MT7629 SoC. | Ryder Lee | |
This patch adds clock modules for MediaTek SoCs: - Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future. - Specific SoC part: the group of structures used to hold the hardware configuration for each SoC. We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> |