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mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.
This commit change the return type of mtk_clk_find_parent_rate to
ulong.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
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This patch fix clock-rate overflow problem in mediatek
clock driver common part.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
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Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
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Add new set_clr_upd mux type and related operation to
mtk common clock driver to support mt8512
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Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
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This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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