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path: root/drivers/clk/rockchip/clk_rk3288.c
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2019-05-01rockchip: use 'arch-rockchip' as header file pathKever Yang
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass
Add support for setting pinctrl and clock for I2S on rk3288. This allows the sound driver to operate. These settings were created by rkmux.py Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-14rockchip: clk: rk3288: handle clk_enable requests for GMACJonathan Gray
Since b0ba1e7e9d9b9441a18048ec67a3b3100c096975 (rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC) Ethernet no longer probes on RK3288. Add no-ops for GMAC clocks observed to be requested which match the clk_enable cases in RK3368 and RK3399. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Cc: Wadim Egorov <w.egorov@phytec.de> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-25rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSICWadim Egorov
The generic ehci-driver (ehci-generic.c) will try to enable the clocks listed in the DTSI. If this fails (e.g. due to clk_enable not being implemented in a driver and -ENOSYS being returned by the clk-uclass), the driver will bail our and print an error message. This implements a minimal clk_enable for the RK3288 and supports the clocks mandatory for the EHCI controllers; as these are enabled by default we simply return success. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk3288: convert to use live dtKever Yang
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28rockchip: clk: guard set_parent implementations against OF_PLATDATAPhilipp Tomsich
The set_parent implementations do not make sense when OF_PLATDATA is enabled. We guard these against OF_PLATDATA and don't populate the set_parent-op when this is the case. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and ↵David Wu
"assign-clock-rate" The RK3288 CRU-node assigns rates to a number of clocks that are not implemented in the RK3288 clock-driver (but which have been sufficiently initialised from rkclk_init()): for these clocks, we implement the gmac clock set parent, but simply ignore the others' set_rate() operation and return 0 to signal success. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-09rockchip: clk: bind reset driverElaine Zhang
Bind rockchip reset to clock-controller with rockchip_reset_bind(). Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: clock: update sysreset driver bindingKever Yang
Using priv for new sysreset driver binding. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: clk: Add SARADC clock support for rk3288David Wu
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13rockchip: clk: remove RATE_TO_DIVKever Yang
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC clock driver. Add or fix the div-field overflow check at the same time. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13rockchip: clk: update dwmmc clock divKever Yang
dwmmc controller has default internal divider by 2, and we always provide double of the clock rate request by dwmmc controller. Sync code for all Rockchip SoC with: 4055b46 rockchip: clk: rk3288: fix mmc clock setting Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-09rockchip: Init clocks again when chain-loadingSimon Glass
Detect with a previous boot loader has already set up the clocks and set them up again so that U-Boot gets what it expects. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09rockchip: rk3288: Convert clock driver to use shifted masksSimon Glass
Shifted masks are the standard approach with rockchip since it allows use of the mask without shifting it each time. Update the definitions and the driver to match. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Rename dev_addr..() functionsSimon Glass
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIOXu Ziyuan
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-16rockchip: clk: rk3288: limit gpll and cpll init to SPL buildHeiko Stübner
The gpll and cpll init values are only used in rk_clk_init in the SPL and therefore produce compile time warnings in regular uboot builds. Fix that with an #ifdef. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
2016-11-25rockchip: clk: Support setting ACLKSimon Glass
Add basic support for setting the ARM clock, since this allows us to run at maximum speed in U-Boot. Currently only a single speed is supported (1.8GHz). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-30rockchip: rk3288: Move rockchip_get_cru() out of the driverSimon Glass
This function is called from outside the driver. It should be placed into common SoC code. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2016-09-22clk: rk3288: add PWM clock get rateKever Yang
This patch add clk_get_rate for PWM device. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-08-05rockchip: remove log2 reimplementation from clock driversHeiko Stübner
The already available ilog2 function does exactly the same in the common case than the log2 function the current clock-driver reimplement. So, simply move to that one. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-08-05move: rockchip: move clock drivers into a subdirectoryHeiko Stübner
With the number of Rockchip clock drivers increasing, don't clutter up the core drivers/clk directory with them and instead move them out of the way into a separate subdirectory. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Updated for rk3399: Signed-off-by: Simon Glass <sjg@chromium.org>
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