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path: root/drivers/clk/rockchip
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2019-07-29rockchip: rk3188: init CPU freq in clock driverKever Yang
Init CPU frquency in clock driver instead of in SPL board file, this will help for use common board file later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki
Add support for setting 400MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki
Add support for setting 50MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19clk: rockchip: rk3399: Fix check patch warnings and checksJagan Teki
- CHECK: spaces preferred around that '*' - CHECK: spaces preferred around that '/' - CHECK: space preferred before that '|' - WARNING: macros should not use a trailing semicolon - CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv' - CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC' - CHECK: Unnecessary parentheses around 'parent->dev == clk->dev' - WARNING: line over 80 characters - CHECK: Prefer kernel type 'u8' over 'uint8_t' - Add proper macro definitions arrangements Note: there are still line over 80 characters and other warnings but fixing those making code look unreadable, so I kept it as it is. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19rockchip: clk: rk3399: handle clk_enable requests for USB3Mark Kettenis
The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30rockchip: clk: rk3399: allow requests for all UART clocksChristoph Muellner
This patch adds the rate for UART1 and UART3 the same way as already implemented for UART0 and UART2. This is required for boards, which have their console output on these UARTs. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: clk: rk322x: fix assert clock valueKever Yang
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add CLK_EMMC_SAMPLE clock supportKever Yang
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-01rockchip: use 'arch-rockchip' as header file pathKever Yang
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: clk: Add mention of four new clocksSimon Glass
These clocks are needed to get MMC running. We don't actually support setting them yet. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass
Add support for setting pinctrl and clock for I2S on rk3288. This allows the sound driver to operate. These settings were created by rkmux.py Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30rockchip: rk3399: Initialize CPU B clock.Christoph Muellner
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz. This decreases the boot time of Linux 4.19 by about 8%. The 600 MHz are inspired by the 600 MHz used for LPLL initialization (came in with commit 9f636a249c1). Tested on RK3399-Q7 on Haikou base board. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30ARM: rockchip: rv1108: Sync clock with vendor treeOtavio Salvador
Make adjustments to the rv1108 clock driver in order to align it with the internal Rockchip version. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay
Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-14rockchip: clk: rk3288: handle clk_enable requests for GMACJonathan Gray
Since b0ba1e7e9d9b9441a18048ec67a3b3100c096975 (rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC) Ethernet no longer probes on RK3288. Add no-ops for GMAC clocks observed to be requested which match the clk_enable cases in RK3368 and RK3399. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Cc: Wadim Egorov <w.egorov@phytec.de> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-25rockchip: rv1108: add ofdata_to_platdata() method for driverKever Yang
Parse of data in dedicated api instead of in probe(). The clk_set_rate() may be called before the clk driver is probed, after core support set default clock. This patch fix system abort issue since: f4fcba5 clk: implement clk_set_defaults() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
2018-04-25rockchip: rk3128: add ofdata_to_platdata() method for driverKever Yang
Parse of data in dedicated api instead of in probe(). The clk_set_rate() may be called before the clk driver is probed, after core support set default clock. This patch fix system abort issue since: f4fcba5 clk: implement clk_set_defaults() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
2018-04-25rockchip: rk3036: add ofdata_to_platdata() method for driverKever Yang
Parse of data in dedicated api instead of in probe(). The clk_set_rate() may be called before the clk driver is probed, after core support set default clock. This patch fix system abort issue since: f4fcba5 clk: implement clk_set_defaults() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSICWadim Egorov
The generic ehci-driver (ehci-generic.c) will try to enable the clocks listed in the DTSI. If this fails (e.g. due to clk_enable not being implemented in a driver and -ENOSYS being returned by the clk-uclass), the driver will bail our and print an error message. This implements a minimal clk_enable for the RK3288 and supports the clocks mandatory for the EHCI controllers; as these are enabled by default we simply return success. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-28rockchip: clk: rk3188: update dpll settings to make EMAC workAlexander Kochetkov
The patch set dpll settings for 300MHz to values used by binary blob[1]. With new values dpll still generate 300MHz clock, but EMAC work. Probably with new values dpll generate more stable clock. dpll on rk3188 provide clocks to DDR and EMAC. With current dpll settings EMAC doesn't work on radxa rock. EMAC sends packets to network, but it doesn't receive anything. ifconfig shows a lot of framing errors. [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk1108: convert to use live dtKever Yang
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk3328: convert to use live dtKever Yang
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk3288: convert to use live dtKever Yang
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk322x: convert to use live dtKever Yang
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk3188: convert to use live dtKever Yang
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk3036: convert to use live dtKever Yang
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-02-24rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLLPhilipp Tomsich
The device-tree node for the PMU clk controller assigns to its parent (i.e. PLL_PPLL) even though this clock currently is set up statically by an init-function. In order to avoid unexpected failures, a simple implementation of set_rate (which accepts requests, but notifies the caller of the preset frequency in its return value) and get_rate (which always returns the preset frequency) are added. Note that this is required for the RK808 PMIC to probe successfully on the RK3399-Q7, following the support for the assigned-clocks property. References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-02-24rockchip: clk: rk3368: handle clk_enable requests for GMACPhilipp Tomsich
Since commit ba1f96672522 ("net: designware: add clock support"), the designware GMAC driver enables all referenced clocks. While this is a no-op for the RK3368 during boot-up (reset behaviour has all the clock gates open anyway), we still need to handle the clock-ids passed in the enable op of the clock-driver and return a success. This change extends the RK3368 clk driver to: (a) provide a enable op (b) signals success to the caller when the clocks for the GMAC are enabled (no actual action is necessary as the gates are open after reset) References: commit ba1f96672522 ("net: designware: add clock support") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-02-24rockchip: clk: rk3399: handle clk_enable requests for GMACPhilipp Tomsich
Since commit ba1f96672522 ("net: designware: add clock support"), the designware GMAC driver enables all referenced clocks. While this is a no-op for the RK3399 during boot-up (reset behaviour has all the clock gates open anyway), we still need to handle the clock-ids passed in the enable op of the clock-driver and return a success. This change extends the enable-op of the rk3399 clk driver to signal success to the caller when the clocks for the GMAC are enabled. References: commit ba1f96672522 ("net: designware: add clock support") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-01-28rockchip: clk: guard set_parent implementations against OF_PLATDATAPhilipp Tomsich
The set_parent implementations do not make sense when OF_PLATDATA is enabled. We guard these against OF_PLATDATA and don't populate the set_parent-op when this is the case. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: clk_rk3368: Implement "assign-clock-parent"David Wu
Implement the setting parent for gmac clock, and add internal pll div set for mac clk. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and ↵David Wu
"assign-clock-rate" The RK3288 CRU-node assigns rates to a number of clocks that are not implemented in the RK3288 clock-driver (but which have been sufficiently initialised from rkclk_init()): for these clocks, we implement the gmac clock set parent, but simply ignore the others' set_rate() operation and return 0 to signal success. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: Add rk322x gamc clock supportDavid Wu
Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: Add rk3328 gamc clock supportDavid Wu
The rk3328 soc has two gmac controllers, one is gmac2io, the other is gmac2phy. We use the gmac2io rgmii interface for 1000M phy here. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28rockchip: clk: rk3399: accept all assigned-clocks from the 'cru'-nodePhilipp Tomsich
The RK3399 CRU-node assigns rates to a number of clocks that are not implemented in the RK3399 clock-driver (but which have been sufficiently initialised from rkclk_init()): for these clocks, we simply ignore the set_rate() operation and return 0 to signal success. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-28rockchip: clk: rk3399: implement set_parent() operationPhilipp Tomsich
This implements the (newly added) set_parent() operation for the RK3399 with a focus on allowing the RGMII clock parent to be configured via the assigned-clock-parents property of the GMAC node. This implementation supports only the GMAC (in fact only the RGMII clock parent) and allows to set this clock's parent either to the internal SCLK_GMAC or to an external clock input (identifiable by it providing a 'clock-output-name' of "gmac_clkin"). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-09rockchip: clk: bind reset driverElaine Zhang
Bind rockchip reset to clock-controller with rockchip_reset_bind(). Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add clock driverKever Yang
Add rk3128 clock driver and cru structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-26rockchip: clk: rk3399: change extract_bits to bitfield_extractPhilipp Tomsich
The RK3399 clk driver still has a left-over use of extract_bits, which can be replaced by using bitfield_extract from include/bitfield.h. This rewrites the invocation to use the shared function. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: clock: update sysreset driver bindingKever Yang
Using priv for new sysreset driver binding. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01rockchip: rk3399: init CPU clock when rkclk_init()Kever Yang
Init the CPU and its buses to speed up the boot time. Move rkclk_init() to a place after rk3399_configure_cpu has defined at the same time, or else there will be a warning. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-01rockchip: rk322x: fix pd_bus hclk/pclkKever Yang
The pd_bus hclk/pclk source is pd_bus aclk, not the PLL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: clk: fix typo in rk322x clock driverKever Yang
Fix typo RK322X/RK3036 in rk322x clock driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: clk: Add rk3399 SARADC clock supportDavid Wu
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: clk: Add rk3368 SARADC clock supportDavid Wu
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: clk: Add rk3328 SARADC clock supportDavid Wu
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: clk: Add SARADC clock support for rk3288David Wu
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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