summaryrefslogtreecommitdiff
path: root/drivers/clk/sunxi
AgeCommit message (Collapse)Author
2019-04-16clk: sunxi: r40: Fix GMAC reset reg offsetJagan Teki
GMAC reset reg offset added by below commit seems to assume it as EMAC but R40 indeed using GMAC. "clk: sunxi: Implement EMAC, GMAC clocks, resets" (sha1: 68620c9698f109c1f001f80d282138a5c67cabef) So, fix by updating the reg offset for RST_BUS_GMAC. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-01clk: sunxi: a10: Add CLK_AHB_GMACJagan Teki
CLK_AHB_GMAC was suppose to be part of previous commit "clk: sunxi: Implement A10 EMAC clocks" add it so-that we can get rid of sunxi_set_gate warning on boot message. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-09clk: sunxi: h3: Implement EPHY CLK and RESETJagan Teki
EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-09clk: sunxi: Implement EMAC, GMAC clocks, resetsJagan Teki
- Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-09clk: sunxi: Implement A10 EMAC clocksJagan Teki
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC. Which would eventually used in sunxi_emac.c driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04clk: sunxi: Implement SPI clocks, resetsJagan Teki
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-30sunxi: clk: enable clk and reset for CCU devicesAndre Przywara
Some Allwinner clock devices have parent clocks and reset gates itself, which need to be activated for them to work. Add some code to just assert all resets and enable all clocks given. This should enable the A80 MMC config clock, which requires both to be activated. The full CCU devices typically don't require resets, and have just fixed clocks as their parents. Since we treat both as optional and enabling fixed clocks is a NOP, this works for all cases, without the need to differentiate between those clock types. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-29sunxi: clk: A80: add MMC clock supportAndre Przywara
The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that. Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: fix a80 mmc clock config compatible] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29sunxi: clk: add MMC gates/resetsAndre Przywara
Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-18clk: sunxi: Add Allwinner A80 CLK driverJagan Teki
Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18clk: sunxi: Add Allwinner H6 CLK driverJagan Teki
Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18clk: sunxi: Implement UART resetsJagan Teki
Implement UART resets for all relevant Allwinner SoC clock drivers via ccu reset table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18clk: sunxi: Implement UART clocksJagan Teki
Implement UART clocks for all Allwinner SoC clock drivers via ccu clock gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18clk: sunxi: Add Allwinner V3S CLK driverJagan Teki
Add initial clock driver for Allwinner V3S. - Implement USB bus and USB clocks via ccu_clk_gate table for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner R40 CLK driverJagan Teki
Add initial clock driver for Allwinner R40. - Implement USB bus and USB clocks via ccu_clk_gate for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A83T CLK driverJagan Teki
Add initial clock driver for Allwinner A83T. - Implement USB bus and USB clocks via ccu_clk_gate table for A83T, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A83T, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A23/A33 CLK driverJagan Teki
Add initial clock driver for Allwinner A23/A33. - Implement USB bus and USB clocks via ccu_clk_gate table for A23/A33, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A23/A33, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A31 CLK driverJagan Teki
Add initial clock driver for Allwinner A31. - Implement USB ahb1 and USB clocks via ccu_clk_gate table for A31, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB ahb1 and USB resets via ccu_reset table for A31, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A10s/A13 CLK driverJagan Teki
Add initial clock driver for Allwinner A10s/A13. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner A10/A20 CLK driverJagan Teki
Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: sunxi: Add Allwinner H3/H5 CLK driverJagan Teki
Add initial clock driver for Allwinner H3/H5. - Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18reset: Add Allwinner RESET driverJagan Teki
Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18clk: Add Allwinner A64 CLK driverJagan Teki
Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
generated by cgit (git 2.34.1) at 2024-12-29 13:15:51 +0000