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2017-08-13rockchip: clk: rk3368: add support for configuring the SPI clocksPhilipp Tomsich
As SPI support may be useful in the boot-flow, this adds support for configuring the SPI controller's clocks in the RK3368 clock driver. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()Philipp Tomsich
With the clock support in rk3368_clk_set_rate() conditionalized on various feature definitions, 'priv' can remain unused (e.g. in the SPL build when only MMC is enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clockPhilipp Tomsich
To enable the GMAC on the RK3368, we need to set up the clocking appropriately to generate a tx_clk for the MAC. This adds an implementation that implements the use of the <&ext_gmac> clock (i.e. an external 125MHz clock for RGMII provided by the PHY). This is the clock setup used by the boards currently supported by U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7). This includes the change from commit - rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)Philipp Tomsich
As part of the DRAM initialisation process (running as part of the TPL stage) on the RK3368, we need to set up the DRAM PLL. This implements support for configuring the PLL to for 1200, 1332 or 1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: clk: rk3368: implement MMC/SD clock reparentingPhilipp Tomsich
The original clock support for MMC/SD cards on the RK3368 suffered from a tendency to select a divider less-or-equal to the the one giving the requested clock-rate: this can lead to higher-than-expected (or rather: higher than supported) clock rates for the MMC/SD communiction. This change rewrites the MMC/SD clock generation to: * always generate a clock less-than-or-equal to the requested clock * support reparenting among the CPLL, GPLL and OSC24M parents to generate the highest clock that does not exceed the requested rate In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup always works), we adjust the driver appropriately. This includes the changes from: - rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: clk: rk3368: implement DPLL (DRAM PLL) supportPhilipp Tomsich
To implement a TPL stage (incl. its DRAM controller setup) for the RK3368, we'll want to configure the DPLL (DRAM PLL). This commit implements setting the DPLL (CLK_DDR) and provides PLL configuration details for the common DRAM operating speeds found on RK3368 boards. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROMPhilipp Tomsich
The RK3368 has a somewhat temperamental BootROM (which I learned the hard way) when it comes to reconfiguring the CPLL and GPLL (in fact, experiments show that changing the GPLL broke things for me, while changing the CPLL seems to be more benign). These should not be modified by the SPL stage, if we intend to return to the BootROM for chain booting the next stage. This commit changes the clock initialisation to not change CPLL/GPLL before returning to the BootROM (i.e. in TPL). As it's safe to change these settings if we no longer intend to return to U-Boot, we'll run the full PLL setup a little later (i.e. in SPL). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driverPhilipp Tomsich
With the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for the SPL stage. This implements support for OF_PLATDATA in the clock driver for the RK3368. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: clk: rk3368: implement bandwidth adjust for PLLsPhilipp Tomsich
The RK3368 TRM recommends to configure the bandwith adjustment (CON2) for PLLs to NF/2. This implements this for all reconfigurations of PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the bandwidth-adjustment feature according to its manual). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13spl: dm: Kconfig: split CLK support for SPL and TPLPhilipp Tomsich
Introduce TPL_CLK to allow finer-grained selection of TPL features for feature-rich (i.e. DM-based) TPL stages. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13spl: dm: Kconfig: SPL_CLK depends on SPL_DMPhilipp Tomsich
SPL_CLK should also depend on SPL_DM (and not just on CLK). Add the additional dependency. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-04Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx changes for v2017.09 Zynq: - Add Z-Turn board support fpga: - Remove intermediate buffer from code Zynqmp: - dts cleanup - change psu_init handling - Add options to get silicon version - Fix time handling - Map OCM/TCM via MMU - Add new clock driver
2017-08-03clk: rmobile: Add RCar Gen3 clock driverMarek Vasut
Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs . This driver allows reading out the clock configuration set by previous boot stages and enabling and disabling clock using the MSTP registers. Setting clock is not supported thus far. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-02clk: zynqmp: Remove unused macros/variablesMichal Simek
These macros and one variable is not used anywhere that's why they should be removed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-02clk: zynqmp: Dont panic incase of mmio write/read failuresSiva Durga Prasad Paladugu
Dont panic incase of mmio write/read failures instead return error and let the peripheral driver take care of clock get and set failures. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-02clk: zynqmp: Add support for CCF driverSiva Durga Prasad Paladugu
Add support for CCF, this CCF reads the ref clocks from dt and checks all the required clock control registers for its source , divisors and calculates the clock from them. This supports clock and set functions. Panic when read/write fails. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28clk: fix compilation errors for poplar platformPatrice Chotard
Move clk_release_all() prototype and definition inside OF_CONTROL flag to avoid following compilation error for poplar platform: aarch64: + poplar +drivers/usb/host/built-in.o: In function `ehci_usb_remove': +drivers/usb/host/ehci-generic.c:159: undefined reference to `clk_release_all' +drivers/usb/host/built-in.o: In function `ehci_usb_probe': +drivers/usb/host/ehci-generic.c:133: undefined reference to `clk_release_all' +make[1]: *** [u-boot] Error 139 +make: *** [sub-make] Error 2 Introduced by 4e542c4 clk: add clk_release_all() Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-28clk: add clk_release_all()Patrice Chotard
Add clk_release_all() method which Disable/Free an array of clocks that has been previously requested by clk_request/get_by_*() Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for ↵Philipp Tomsich
auto-alloc The clk driver for the RK3368 picked the wrong data structure's size for its auto-alloc size: the size was calculated on the structure representing the CRU hardware block instead of the priv structure. As the CRU's register file is much larger than the driver's priv, this did not cause any pain (except wasting memory). Fix this by using the correct data structure's size. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26clk: stm32f7: remove clock_get()Patrice Chotard
All drivers which was using clock_get() are now using clk_get_rate() from clock framework, now it's safe to remove clock_get(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26clk: stm32f7: cleanup clocks unused definitionsPatrice Chotard
clean the code by removing unused enums, structs and defines related to clocks Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26clk: stm32f7: add clock .get_rate() callbackPatrice Chotard
Add clock framework .get_rate callback. This step will allow to convert all drivers which was using proprietary clock_get() to use clock framework .get_rate(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26clk: stm32f7: get RCC base address from DTPatrice Chotard
Retrieve RCC base address from DT, this will prepare the ground for future STM32 SoCs support. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26clk: stm32f7: add static for configure_clocks()Patrice Chotard
Also remove its declaration from stm32.h which is no more needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-11rockchip: rk322x: add clock driverKever Yang
Add clock driver init support for: - cpu, bus clock init; - emmc, sdmmc clock; - ddr clock; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixed format specified (%x -> %p) in clk_rk322x.c: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-24Merge git://git.denx.de/u-boot-uniphierTom Rini
- fix sparse warnings - sync DT with Linux - add new board support (LD11/LD20 global)
2017-06-25ARM: uniphier: fix various sparse warningsMasahiro Yamada
Fix warnings reported by sparse: - ... was not declared. Should it be static?" - cast to restricted __be32 While fixing those, the type conflict of cci500_init() was found. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-23Merge branch 'master' of git://git.denx.de/u-boot-rockchipTom Rini
2017-06-23rockchip: clk: rk3036: correct setting for pll integer modeKever Yang
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll integer mode, while the '0' means the frac mode. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-23clk_rv1108.c: Fix unused variable warningTom Rini
The variables gpll_init_cfg and apll_init_cfg are unused in this file, remove them. Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09rockchip: Init clocks again when chain-loadingSimon Glass
Detect with a previous boot loader has already set up the clocks and set them up again so that U-Boot gets what it expects. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09rockchip: rk3288: Convert clock driver to use shifted masksSimon Glass
Shifted masks are the standard approach with rockchip since it allows use of the mask without shifting it each time. Update the definitions and the driver to match. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: clk: Add rv1108 clock driverAndy Yan
Add clock driver support for Rockchip rv1108 soc Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: clock: rk3036: some fix according TRMKever Yang
- hclk/pclk_div range should use '<=' instead of '<' - use GPLL for pd_bus clock source - pd_bus HCLK/PCLK clock rate should not bigger than ACLK Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3036: clean mask definition for cru regKever Yang
Embeded the shift in mask MACRO definition in cru header file and clock driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3368: Add clock driverAndy Yan
Add driver to setup the various PLLs and peripheral clocks on the RK3368. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: clk: fixed: Update to support livetreeSimon Glass
Update the fixed-rate clock driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: clk: Update uclass to support livetreeSimon Glass
Update the clk uclass to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01clk: Modify xlate() method for livetreeSimon Glass
Update the xlate() method to use ofnode_phandle_args instead of the fdtdec variant. This will allow drivers to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: core: Update device_bind_driver_to_node() to use ofnodeSimon Glass
Adjust this function to us an ofnode instead of an offset, so it can be used with livetree. This involves updating all callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: core: Replace of_offset with accessor (part 2)Simon Glass
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Rename dev_addr..() functionsSimon Glass
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Use dm.h header when driver mode is usedSimon Glass
This header includes things that are needed to make driver build. Adjust existing users to include that always, even if other dm/ includes are present Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-10Merge git://git.denx.de/u-boot-rockchipTom Rini
This adds a new firefly-rk3399 board, MIPI support for rk3399 and rk3288, rk818 pmic support, mkimage improvements for rockchip and a few other things.
2017-05-10rockchip: clk: rk3399: allow requests for HDMI clocksPhilipp Tomsich
This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF, which are clock gates in the HDMI output path for the RK3399. As these are enabled by default (i.e. after reset), we don't implement any logic to actively open/close these clock gates and simply assume that their reset-default has not been changed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NSPhilipp Tomsich
The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS. To allow us to add a efuse-driver (and more importantly, to allow probes of such a driver to succeed), we need need to accept requests for PCLK_EFUSE1024NS and return a non-error result. As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't implement any logic to manage this clock gate and simply assume that the reset-default has not been changed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTSPhilipp Tomsich
The clocking of the designware MMC controller in the upstream (i.e. Linux) RK3399 has changed/does not match what the current DTS in U-Boot uses: the first clock entry now is HCLK_SDMMC instead of SCLK_SDMMC. With the simple clock driver used for the RK3399, this needs a change in the selector understood by the various case statements in the driver to ensure that the driver still loads successfully. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3399: fix off-by one during rate calculation in ↵Philipp Tomsich
i2c/spi_set_rate For the RK3399, i2c_set_rate (and by extension: our spi_set_rate, which had been mindlessly following the template of the i2c_set_rate implementation) miscalculates the rate returned due to a off-by-one error resulting from the following sequence of events: 1. calculates 'src_div := src_freq / target_freq' 2. stores 'src_div - 1' into the register (the actual divider applied in hardware is biased by adding 1) 3. returns the result of the DIV_RATE(src_freq, src_div) macro, which expects the (decremented) divider from the hardware-register and implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)') This can be observed with the SPI driver, which sets a rate of 99MHz based on the GPLL frequency of 594MHz: the hardware generates a clock of 99MHz (src_div is 6, the bitfield in the register correctly reads 5), but reports a frequency of 84MHz (594 / 7) on return. To fix, we have two options: * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't make for a particularily nice read * we simply call the i2c/spi_get_rate function (introducing additional overhead for the additional register-read), which reads the divider from the register and then passes it through the DIV_RATE macro Given that this code is not time-critical, the more readable solution (i.e. calling the appropriate get_rate function) is implemented in this change. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5Philipp Tomsich
This change adds support for configuring the module clocks for SPI1 and SPI5 from the 594MHz GPLL. Note that the driver (rk_spi.c) always sets this to 99MHz, but the implemented functionality is more general and will also support different clock configurations. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMCXu Ziyuan
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>