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path: root/drivers/clk
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2020-01-14clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USBGiulio Benetti
div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocksGiulio Benetti
Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx8qxp: extend to support getting I2C IPG clockAnatolij Gustschin
Since commit d02be21d3004 ("i2c: imx_lpi2c: add ipg clk") getting I2C clocks doesn't work. Add I2C IPG clock IDs to related switch statements to fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-09Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xxTom Rini
- A small PR with MC8309 fixes from Rasmus.
2020-01-09Merge tag 'dm-pull-8jan20' of git://git.denx.de/u-boot-dmTom Rini
dm: Increased separation of ofdata_to_platdata() and probe methods
2020-01-08Merge tag 'efi-2020-04-rc1' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-04-rc1 This pull request provides: * support for FIT images for UEFI binaries * drivers for hardware random number generators * an implementation of the EFI_RNG_PROTOCOL * a sub-command for efidebug to display configuration tables
2020-01-08Merge tag 'u-boot-imx-20200108' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx --------------------------------------------------------------------- Add i.MX8MP SoC and EVK board Update README for i.MX8MN EVK and fix mmc env Add pca9450 driver -------------------------------------------------------------------- Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885
2020-01-08clk: imx: add i.MX8MP clk driverPeng Fan
Add i.MX8MP clk driver for i.MX8MP CLK driver model usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08clk: imx: add imx_clk_mux2_flagsPeng Fan
Add imx_clk_mux2_flags which will be used by i.MX8MP Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08mpc83xx_clk: always treat MPC83XX_CLK_PCI as invalidRasmus Villemoes
The current mpc83xx_clk driver is broken for any board for which mpc83xx_has_pci() is true, i.e. anything not MPC8308: When is_clk_valid() reports that MPC83XX_CLK_PCI is valid, init_all_clks() proceeds to call init_single_clk(), but that doesn't know about either MPC83XX_CLK_PCI or has any handling of the TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence init_single_clk() ends up returning -EINVAL, and the whole board hangs in serial_init(). The quickest fix is to simply pretend that clock is invalid for all, since nobody can have been relying on it. Adding proper support seems to be a bit more involved than just handling TYPE_SCCR_ONOFF: - The power-on-reset value of SCCR[PCICM] is 0, so mpc83xx_clk_enable() would probably need to be tought to enable the clock. - The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2 depending on the CFG_CLKIN_DIV configuration input, but that can't be read from software, so to properly fill out ->speed[MPC83XX_CLK_PCI] I think one would need guidance from Kconfig or dtb. Partially fixes: 07d538d281 clk: Add MPC83xx clock driver Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Mario Six <mario.six@gdsys.cc>
2020-01-07aspeed: ast2500: Read clock ofdata in the correct methodSimon Glass
At present the clock driver reads its ofdata in the probe() method. This is not correct although it is often harmless. However in this case it causes a problem, something like this: - ast_get_scu() is called (from somewhere) to get the SCI address - this probes the clock - first sets up ofdata (which does nothing at present) - DM marks clock device as active - DM calls pinctrl - pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe() - ast_get_scu() probes the clock, but sees it already marked as probed - ast_get_scu() accesses the clock's private data, with scu as NULL - DM calls clock probe function ast2500_clk_probe() which reads scu By putting the read of scu into the correct method, scu is read as part of ofdata setup, and everything is OK. Note: This problem did not matter until now since DM always probed all parents before reading a child's ofdata. The fact that pinctrl is a child of clock seems to trigger this strange bug. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-01-07clk: stm32mp1: Add a clock entry for RNG1 deviceSughosh Ganu
Add an entry for allowing clock enablement for the random number generator peripheral, RNG1. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07clk: agilex: Add clock driver for AgilexLey Foon Tan
Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-12-09Merge tag 'u-boot-imx-20191209' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.01 ----------------- - imx8qxp_mek: increase buffer sizes and args number - Fixes for imx7ulp - imx8mm: Fix the first root clock in imx8mm_ahb_sels[] - colibri_imx7: reserve DDR memory for Cortex-M4 - vining2000: fixes and convert to ethernet DM - imx8m: fix rom version check to unbreak some B0 chips - tbs2910: Disable VxWorks image booting support
2019-12-06clk: imx: imx8mm: Fix the first root clock in imx8mm_ahb_sels[]Frieder Schrempf
The 24MHz oscillator clock is referenced by "clock-osc-24m" and not "osc_24m". Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-12-03clk: mediatek: add driver for MT8518mingming lee
Add clock driver for MediaTek MT8518 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-02common: Move get_ticks() function out of common.hSimon Glass
This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02Move strtomhz() to vsprintf.hSimon Glass
At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-17rockchip: clk: Add clk driver for rk3308Finley Xiao
Add clk controller driver for RK3308 SOC. This patch depends on Elaine's pll patch[0]. [0]http://patchwork.ozlabs.org/patch/1183718/ Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: pll: add common pll setting funcsElaine Zhang
Common PLL setup function, compatible with different SOC. Mainly for the subsequent new SOC use. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: fix wrong CONFIG_IS_ENABLED handlingHeiko Stuebner
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so without the leading CONFIG_. The clock drivers all wrongly check for CONFIG_RESET_ROCKCHIP, fix that Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: rv1108: remove duplicate reset initHeiko Stuebner
rockchip_reset_bind() already does the needed init for the reset registers, only referenced the wrong cru structure. So we can get rid of the open-coded reset init and just fix the correct cru reference. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: add px30 clock driverKever Yang
The px30 contains 2 separate clock controllers, pmucru and cru. Add drivers for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-12Merge tag 'u-boot-imx-20191105' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191105 ------------------- i.MX8MN SoC support ROM API image download support i.MX8MM enet enabling
2019-11-11Merge tag 'u-boot-rockchip-20191110' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Add support for rockchip pmic rk805,rk809, rk816, rk817 - Add rk3399 board Leez support - Fix bug in rk3328 ram driver - Adapt SPL to support ATF bl31 with entry at 0x40000 - Fix the u8 type comparision with '-1'. - Fix checkpatch warning for multi blank line and review signature.
2019-11-10clk: rockchip: rk3328: Configure CPU clockSimon South
Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-07clk: clk-ti-sci: Notify AVS driver upon setting clock rateKeerthy
Notify AVS driver upon setting clock rate so that voltage is changed accordingly. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-05clk: imx: imx8mm: add set_parent callbackPeng Fan
Add set_parent callback, then assigned-clock-parents in dts could be work. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05clk: imx8mm: add enet clkPeng Fan
Add enet ref/timer/PHY_REF/root clk which are required to make enet function well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05clk: imx: add i.MX8MN ccf driverPeng Fan
Add i.MX8MM ccf driver support. Modifed from Linux Kernel 5.3.0-rc1, drop some entries that not used in U-Boot and adapt to U-Boot CCF style. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Lukasz Majewski <lukma@denx.de>
2019-10-30Merge tag 'u-boot-clk-23Oct2019' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Add I2C clocks for i.MX6Q CCF driver - Fix check in clk_set_default_parents() - Managed API to get clock from device tree - Fixes for core clock code (including sandbox regression tests)
2019-10-25Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsTom Rini
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
2019-10-25clk: add clock driver for MediaTek MT76x8 platformWeijie Gao
This patch adds a clock driver for MediaTek MT7628/7688 SoC. It provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-24arm64: zynqmp: Switch to xlnx-zynqmp-clk headerMichal Simek
Use prepared header instead of hardcoded values. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: versal: Rename versal_pm_request to xilinx_pm_requestMichal Simek
Use generic name instead of Versal specific because this should be also used on ZynqMP. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: versal: Clean pm_api_id usageMichal Simek
Copy enum values from platform code to firmware code. IDs are shared between ZynqMP and Versal. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-22test: clk: test clock self assignmentJean-Jacques Hiblot
Make sure that the clock self-assignment works by having a clock of clk-sbox be configured automatically when clk-sbox is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22drivers: clk: Fix using assigned-clocks in the node of the clock it sets upJean-Jacques Hiblot
This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22test: clk: Update tests to also check the managed APIJean-Jacques Hiblot
Add a few more clocks the clk_sandbox clock provider and get them using the managed API. Make sure they are released when the device is removed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22drivers: clk: Add a managed API to get clocks from the device-treeJean-Jacques Hiblot
Add devm_clk_get(), devm_clk_get_optional() to get clocks from the device-tree. The clocks is automatically released and the data structure freed when the device is unbound. Also add devm_clk_put() to release the clock and free the data structure manually. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22drivers: clk: Handle gracefully NULL pointersJean-Jacques Hiblot
Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22clk: Add support for I2C clocks on NXP's imx6q SoC which use CCFLukasz Majewski
This change adds support for I2C clock modeled in CCF. This code intention is to only enable those clocks in the I2C driver with default settings. For that reason the "busy" versions of clocks reuse the generic approach and would need to be updated when one wants to adjust the I2C clock frequency in U-Boot. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-22clk: Fix error check in clk_set_default_parents()Jean-Jacques Hiblot
According to the documentation in clk.h, clk_set_parent() return the new rate of the clock or a negative error code. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-18clk: meson-sm1: add compatibleNeil Armstrong
The SM1 clock controller is almost identical to the G12A and so far the differences don't matter. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18clk: meson: g12a: add support for VPU/HDMI clocksNeil Armstrong
Add necessary clock support to set up clock for the VPU and HDMI support. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-11clk: cdce9xx: add support for cdce9xx clock synthesizerTero Kristo
Add support for CDCE913/925/937/949 family of devices. These are modular PLL-based low cost, high performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. The initial version of the driver does not support programming of the PLLs, and thus they run in the bypass mode only. The code is loosely based on the linux kernel cdce9xx driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-09Merge tag 'xilinx-for-v2020.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file
2019-10-08clk: versal: Add clock driver supportSiva Durga Prasad Paladugu
This patch adds clock driver support for Versal platform. The clock driver queries and performs clock operations using PLM firmware by communicating with it using SMC calls. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08zynqmp: firmware: Add Xilinx ZynqMP firmware driverRajan Vaja
Add simple ZynqMP firmware drive to populate child nodes under zynqmp_firmware DT node. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08ARM: at91: Rename sama5_sfr.h to at91_sfr.hTudor Ambarus
The Special Function Registers (SFR) are present in sam9x5 and sam9x60 too, rename sama5_sfr to at91_sfr.h. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
generated by cgit (git 2.34.1) at 2025-01-12 18:29:20 +0000