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Add devm_clk_get(), devm_clk_get_optional() to get clocks from the
device-tree. The clocks is automatically released and the data structure
freed when the device is unbound.
Also add devm_clk_put() to release the clock and free the data structure
manually.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
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Prepare the way for a managed CLK API by handling NULL pointers without
crashing nor failing.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
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This change adds support for I2C clock modeled in CCF. This code intention
is to only enable those clocks in the I2C driver with default settings.
For that reason the "busy" versions of clocks reuse the generic approach
and would need to be updated when one wants to adjust the I2C clock
frequency in U-Boot.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
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According to the documentation in clk.h, clk_set_parent() return the new
rate of the clock or a negative error code.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
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The SM1 clock controller is almost identical to the G12A and
so far the differences don't matter.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Add necessary clock support to set up clock for the VPU and
HDMI support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
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Add support for CDCE913/925/937/949 family of devices. These are modular
PLL-based low cost, high performance, programmable clock synthesizers,
multipliers and dividers. They generate up to 9 output clocks from a
single input frequency. The initial version of the driver does not
support programming of the PLLs, and thus they run in the bypass mode
only. The code is loosely based on the linux kernel cdce9xx driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx/FPGA changes for v2020.01
FPGA:
- Enable fpga loading on Versal
- Minor fix
Microblaze:
- Fix LMB configurations to support initrds
- Some other cleanups
Zynq:
- Minor config/dt changes
- Add distro boot support for usb1 and mmc1
- Remove Xilinx private boot commands and use only distro boot
ZynqMP:
- Kconfig cleanups, defconfig updates
- Update some dt files
- Add firmware driver for talking to PMUFW
- Extend distro boot support for jtag
- Add new IDs
- Add system controller configurations
- Convert code to talk firmware via mailbox or SMCs
Versal:
- Add board_late_init()
- Add run time DT memory setup
- Add DFU support
- Extend distro boot support for jtag and dfu
- Add clock driver
- Tune mini configurations
Xilinx:
- Improve documentation (boot scripts, dt binding)
- Enable run time initrd_high calculation
- Define default SYS_PROMPT
- Add zynq/zynqmp virtual defconfig
Drivers:
- Add Xilinx mailbox driver for talking to firmware
- Clean zynq_gem for Versal
- Move ZYNQ_HISPD_BROKEN to Kconfig
- Wire genphy_init() in phy.c
- Add Xilinx gii2rgmii bridge
- Cleanup zynq_sdhci
- dwc3 fix
- zynq_gpio fix
- axi_emac fix
Others:
- apalis-tk1 - clean config file
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This patch adds clock driver support for Versal platform. The clock driver
queries and performs clock operations using PLM firmware by communicating
with it using SMC calls.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Add simple ZynqMP firmware drive to populate child nodes under
zynqmp_firmware DT node.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Add code to enable the SD clock on the ast2500 SoC.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- add missing g12b clock driver compatible, fixing odroid-n2 usb support
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The G12B clock controller is almost identical to the G12A and
so far the differences don't matter. Adding the G12B compatible
makes USB work on the Odroid-N2.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Use existing gd structure to store frequency information
which can be used in drivers or arch without new request.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Remove many debug trace.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Several options are presenting themselves on a various boards
where the options are clearly not used. (ie, SPL/TPL options
when SPL or TPL are not defined)
This patch is not attempting to be a complete list of items, but
more like low hanging fruit. In some instances, I wasn't sure
of DM was required, so I simply made them SPL or TPL.
This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.
Signed-off-by: Adam Ford <aford173@gmail.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- remove rk3288 fennec board
- remove SPL raw image support for Rockchip SoCs
- add common misc_init_r() for ethaddr from cpuid
- enable USB HOST support for rk3328
- unify code for finding a valid gpt in part driver
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Required to successfully probe the ehci generic driver
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Add i.MX8MM clk driver support.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add pll14xx driver for i.MX8MM usage, modifed
from Linux Kernel 5.3.0-rc1
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Expose CCF entry, then we could avoid expand the SoC support list
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Since we added clk enable_count and prograte clk child enabling
operation to clk parent, so add a new function sandbox_clk_enable_count
to get enable_count for test usage.
And add test code to get the enable_count after we enable/disable
the device clk.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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On i.MX8MM, thinking such as clk path
OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device
Only enabling CCGR GATE is not enough, we also need to enable PLL GATE
to make sure the clk path work. So when enabling CCGR GATE,
we could prograte to enabling PLL GATE to make life easier.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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As what Linux Kernel 5.3.0 provides when enable/disable clk,
there is an enable_count in clk_core_disable/enable. Introduce
enable_count to track the clk enable/disable count when
clk_enable/disable for CCF. And Initialize enable_count to 0 when
register the clk.
And clk tree dump with enable_count will be supported, it will
be easy for us to check the clk status with enable_count
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add support for clk_is_match() which is required to
know if two clock pointers point to the same exact
physical clock.
Also add a unit test for the new API.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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This adds high speed interface subsystem - hifsys (i.e. PCIe and USB)
for MT7623 SoC and enables its reset controller.
The control block is shared with ethsys and accordingly rename the
related defines.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
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- Port more CCF code to work with i.MX8 devices.
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First thing we check in meson_clk_set_rate_by_id() is current_rate == rate.
There is not need to check it again.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Add composite clk to sandbox driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Introduce io_gate_val for sandbox clk gate test usage
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Import clk composite clk support from Linux Kernel 5.1-rc5
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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When the device not binded with a node, we need ignore
the parents and rate settings.
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add set rate for imx clk-gate2
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Import some clk helpers from Linux Kernel for i.MX8MM usage
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Export the structure for others to use.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Import clk-gate support from Linux Kernel 5.1-rc5
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add set parent support for clk mux
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Preparing to support composite clk.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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When support Clock Common Framework, U-Boot use dev for
clk tree information, there is no clk->parent. When
support composite clk, it contains mux/gate/divider,
but the mux/gate/divider is not binded with device.
So we could not use dev_get_uclass_priv to get the correct
clk_mux/gate/divider. So add clk_dev_binded to let
choose the correct method.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean up and migrate to use common rockchip spl board file
- Clean up and migrate to use common rockchip board file
- Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
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Init CPU frquency in clock driver instead of in SPL board file,
this will help for use common board file later.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20190719
- CCF for i.MX6
- nandbcb command to write SPL into NAND
- Switch to DM (i.MX28)
- Boards: Toradex, engicam, DH
- Fixes for i.MX8
- Fixes for i.MX7ULP
Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
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