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path: root/drivers/clk
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2019-07-10clk: uniphier: add EMMC clock for LD11, LD20, and PXs3Masahiro Yamada
I also added comments for NAND clocks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-11Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-bootTom Rini
- Add Ethernet support for STM32MP1 - Add saveenv support for STM32MP1 - Add STM32MP1 Avenger96 board support - Add SPI driver suport for STM32MP1 - Add watchdog support for STM32MP1 - Update power supply check via USB TYPE-C for STM32MP1 discovery board
2019-06-11clk: imx8qm: fix usdhc2 clocksMarcel Ziswiler
Trying to bring up uSDHC2 the following error message was observed: MMC: imx8_clk_set_rate(Invalid clk ID #60) imx8_clk_set_rate(Invalid clk ID #60) usdhc@5b030000 - probe failed: -22 This commit fixes this by properly setting resp. clocks. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-06-06stm32mp1: clk: use the correct identifier for ethckPatrick Delaunay
ETHCK_K is the identifier the kernel clock for ETH in kernel binding, selected by ETHKSELR / gated by ETHCKEN = BIT(7). U-Boot driver need to use the same identifier, so change ETHCK to ETHCK_K. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
2019-06-06clk: stm32mp1: Add SPI1 clock entryPatrice Chotard
Add missing SPI1 clock needed by SPI1 instance. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-06-01clk: sifive: Add clock driver for GEMGXL MGMTBin Meng
This adds a clock driver to support the GEMGXL management IP block found in FU540 SoCs to control GEM TX clock operation mode for 10/100/1000 Mbps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-05-31Merge tag 'rockchip-for-v2019.07-rc3' of git://git.denx.de/u-boot-rockchipTom Rini
- some fix for rk3399-puma; - rockchip script make_fit_atf.py cleanup - Enable TPL for rk3399 orangepi and nanopi4; - add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
2019-05-31clk: meson-g12a: Add PCIE PLL supportNeil Armstrong
The G12A PCIE PLL clock was introduced in Linux 5.2-rc1, and is needed for USB to operate, add basic support for it and associated gates. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-05-30rockchip: clk: rk3399: allow requests for all UART clocksChristoph Muellner
This patch adds the rate for UART1 and UART3 the same way as already implemented for UART0 and UART2. This is required for boards, which have their console output on these UARTs. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-23clk: stm32mp1: add set_rate for DDRPHYC clockPatrick Delaunay
Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-21mpc83xx_clk: Add enable methodMario Six
Some DM drivers have hardcoded clk_enable calls when handling clocks (for example the fsl_esdhc driver). To work with these drivers, add an enable method to the MCP83xx clock driver (which does nothing, because the clocks are always enabled). Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-09Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchipTom Rini
Improvements and new features: - split more rockchip pinctrl_core feature into per SoC - enable TPL for evb-rk3399 board - enable TPL/SPL for evb-px5 board - enable TPL and OP-TEE support for evb-rk3229 - update fix in arm common assembly start code for rockchip header file - update default SPL_FIT_GENERATOR for rockchip - rk3399 boards update to use '-u-boot.dtsi' - add new rk3399 boards: Nanopi M4, Nanopc T4 - enable sound for chromebook_minnie
2019-05-08Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
- H6 Beelink GS1 board (Clément) - Olimex A64-Teres-I board (Jonas) - sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej) - Change include order (Jagan) - EPHY clock changes (Jagan) - EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
2019-05-09clk: Use clk_get_by_index_tail()Jagan Teki
clk_get_by_index_tail() now handle common clk get by index code so use it from clk_get_by_indexed_prop(). Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09clk: Get the CLK by index without deviceJagan Teki
Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-09clk: sifive: fu540-prci: Change include orderJagan Teki
Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the fu540-prci driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from include/clk-uclass.h:13, from drivers/clk/sifive/fu540-prci.c:32: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in fu540-prci.c to include first common.h file. Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-08rockchip: clk: rk322x: fix assert clock valueKever Yang
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add CLK_EMMC_SAMPLE clock supportKever Yang
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-01Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchipTom Rini
Improvements and new features: - improved SPI driver for better read throughput - refactors initialisation of debug UART init - restructures header file paths - adds pinctrl improvements Adds Kever as a co-custodian.
2019-05-01Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imxTom Rini
Porting to DM and i.MX8 ------------------------ - warp7 to DM - kp_imx53 to DM - Warnings in DT - MX8QM support - colibri-imx6ull to DM - imx7d-pico to DM - ocotp for MX8
2019-05-01rockchip: use 'arch-rockchip' as header file pathKever Yang
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-04-25clk: imx8: add i.MX8QM clk driverPeng Fan
Add i.MX8QM clk driver, SDHC/FEC/UART/I2C supported. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25clk: imx8: split code into common and soc specific partPeng Fan
To make it easy to add new clk driver for i.MX8, split the code into common part and SoC specific part. Make the get/set/enable non static and introduce a num_clks for soc_clk_dump, because the arrays are moved to clk-imx8qxp.c. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-24Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogicTom Rini
- Add support for Amlogic p200 & p201 Reference Designs - Add Amlogic SoC information display - Add support for the Libretech-AC AML-S805X-AC board - Add Amlogic AXG reset compatible - Add I2C support for Amlogic AXG - Fix AXG PIN and BANK pinctrl definitions - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset - Add initial support for Amlogic G12A SoC and U200 board - Enable PHY_REALTEK for selected boards - Fix Khadas VIM2 README
2019-04-23clk: mediatek: add driver for MT8516Fabien Parent
Add clock driver for MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com> [trini: Redo whitespace] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-23clk: mediatek: add support for SETCLR_INV and NO_SETCLR flagsFabien Parent
Add the implementation for the CLK_GATE_SETCLR_INV and CLK_GATE_NO_SETCLR flags. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23clk: meson: add g12a supportJerome Brunet
Add basic support for the Amlogic G12A clock controller based on the AXG driver. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23clk: create meson directory and move related driversJerome Brunet
In order to support the Amlogic G12A clock controller, re-architect the clock files into a meson directory. No functionnal changes. MAINTAINERS entry is also updated. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-17Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
- Convert DM_MMC and DM_SCSI - A20, R40, H6 Linux dts(i) sync - CLK, RESET support for sunxi, sun8_emac net drivers
2019-04-16clk: sunxi: r40: Fix GMAC reset reg offsetJagan Teki
GMAC reset reg offset added by below commit seems to assume it as EMAC but R40 indeed using GMAC. "clk: sunxi: Implement EMAC, GMAC clocks, resets" (sha1: 68620c9698f109c1f001f80d282138a5c67cabef) So, fix by updating the reg offset for RST_BUS_GMAC. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-16ARM: zynq: Add missing i2c get_rate for fixing i2c SPLHannes Schmelzer
The commit 'f48ef0d81aa837a33020f8d61abb3929ba613774' did break I2C support because requesting the clock for the I2C ip-block isn't supported during SPL. To fixup this we add support requesting clocks for: - i2c0 - i2c1 Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-13Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dmTom Rini
fdtdec tests and improvements for carve-outs pinctrl race-condition fix various other fixes in sandbox, sound, mkimage, etc.
2019-04-12Merge tag 'u-boot-stm32-20190412' of https://github.com/patrickdelaunay/u-bootTom Rini
stm32 patches for v2019.07-rc1 - Add trusted boot with TF-A for stm32mp1 - stm32mp1 dts files sync'ed with Linux version - add STM32MP1 Discovery boards (DK1 and DK2) - add STMFX gpio expander driver - misc improvement for stm3mp1 supports - rename stpmu1 to stpmic1 (official name) - stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu) - add STM32 FMC2 NAND flash controller driver
2019-04-12stm32mp1: add trusted boot with TF-APatrick Delaunay
Add support of trusted boot, using TF-A as first stage bootloader, The boot sequence is BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32 The TF-A monitor provides secure monitor with support of SMC - proprietary to manage secure devices (BSEC for example) - PSCI for power The same device tree is used for STMicroelectronics boards with basic boot and with trusted boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-11clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay
Prepare to remove dm_fdt_pre_reloc function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11clk: at91: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay
Prepare to remove dm_fdt_pre_reloc Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-09clk: renesas: Synchronize Gen3 tables with Linux 5.0Marek Vasut
Synchronize R-Car Gen3 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Synchronize Gen2 tables with Linux 5.0Marek Vasut
Synchronize R-Car Gen2 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Add R8A77965 clock tablesMarek Vasut
Add clock tables for R8A77965 from Linux 5.0 , except for the crit, R and Z clock, which are neither used nor supported by the U-Boot clock framework yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-01clk: sunxi: a10: Add CLK_AHB_GMACJagan Teki
CLK_AHB_GMAC was suppose to be part of previous commit "clk: sunxi: Implement A10 EMAC clocks" add it so-that we can get rid of sunxi_set_gate warning on boot message. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-25clk: renesas: Add support for setting MMCIF clock divider on Gen2Marek Vasut
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms. This allows the MMCIF driver to set higher clock rate if desired. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25clk: renesas: Fix swapped div and mul in debug output on Gen2Marek Vasut
The $div and $mul values were swapped in the debug output, fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25clk: renesas: Fix SDH clock divider decoding on Gen2Marek Vasut
The gen2_clk_get_sdh_div() function is supposed to look up the $val value read out of the SDCKCR register in the supplied table and return the matching divider value. The current implementation was matching the value from SDCKCR on the divider value in the table, which is wrong. Fix this and rework the function a bit to make it more readable. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-09clk: sunxi: h3: Implement EPHY CLK and RESETJagan Teki
EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-09clk: sunxi: Implement EMAC, GMAC clocks, resetsJagan Teki
- Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-09clk: sunxi: Implement A10 EMAC clocksJagan Teki
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC. Which would eventually used in sunxi_emac.c driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04clk: sunxi: Implement SPI clocks, resetsJagan Teki
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-02-28Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Gen2/Gen3 fixes for warnings and sdhi
2019-02-27clk: Add fixed-factor clock driverAnup Patel
This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27clk: Add SiFive FU540 PRCI clock driverAnup Patel
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
generated by cgit (git 2.34.1) at 2024-12-28 16:49:00 +0000