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path: root/drivers/clk
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2019-07-29Merge tag 'u-boot-rockchip-20190729' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Clean up and migrate to use common rockchip spl board file - Clean up and migrate to use common rockchip board file - Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
2019-07-29rockchip: rk3188: init CPU freq in clock driverKever Yang
Init CPU frquency in clock driver instead of in SPL board file, this will help for use common board file later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-27Merge tag 'u-boot-imx-20190719' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20190719 - CCF for i.MX6 - nandbcb command to write SPL into NAND - Switch to DM (i.MX28) - Boards: Toradex, engicam, DH - Fixes for i.MX8 - Fixes for i.MX7ULP Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
2019-07-24clk: initialize clk->data when using default xlateSekhar Nori
Right now when using clk_of_xlate_default(), clk->data remains un-initialized because clk_get_bulk() does not initialize memory on allocation of clock structure. This can cause problems when data is used to match if two clocks pointers are exactly the same underlying clocks, for example. Fix it by initializing clk->data to 0. Suggested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-07-23Merge tag 'u-boot-stm32-20190723' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - add rtc driver for stm32mp1 - add remoteproc driver for stm32mp1 - use kernel qspi compatible string for stm32
2019-07-22clk: stm32mp1: Add RTC clock entryPatrick Delaunay
Add RTCAPB and RTC clock support. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-21Merge tag 'rockchip-for-v2019.07' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3399 lpddr4 support - rk3399-rock960 board support improvement - Eliminate pyelftools dependency by make_fit_atf.py - clean up rockchip dts to use -u-boot.dtsi - use ARM arch/generic timer instead of rk_timer - clean up Kconfig options for board support
2019-07-21clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki
Add support for setting 400MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki
Add support for setting 50MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]Lukasz Majewski
This patch provides code to implement the CCF clock tree in sandbox. It uses all the introduced primitives; some generic ones are reused, some sandbox specific were developed. In that way (after introducing the real CCF tree in sandbox) the recently added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested in their natural work environment. Usage (sandbox_defconfig and sandbox_flattree_defconfig): ./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf" Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19clk: sandbox: Adjust clk-mux.c to emulate reading divider value from HWLukasz Majewski
The generic mux clock code for CCF requires reading the clock multiplexer value from HW registers. As sandbox by design has readl() as no-op it was necessary to provide this value in the other way. The new field in the mux structure (accessible only when sandbox is run) has been introduced for this purpose. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19clk: sandbox: Adjust clk-divider to emulate reading its value from HWLukasz Majewski
The generic divider clock code for CCF requires reading the divider value from HW registers. As sandbox by design has readl() as no-op it was necessary to provide this value in the other way. The new field in the divider structure (accessible only when sandbox is run) has been introduced for this purpose. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flagLukasz Majewski
If the CLK_GET_RATE_NOCACHE flag is set - the clk_get_parent_rate() provides recalculated clock value without considering the cache setting. This may be necessary for some clocks tightly coupled with power domains (i.e. imx8), and prevents from reading invalid cached values. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)Lukasz Majewski
This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19dm: clk: Define clk_get_by_id() for clk operationsLukasz Majewski
This commit adds the clk_get_by_id() function, which is responsible for getting the udevice with matching clk->id. Such approach allows re-usage of inherit DM list relationship for the same class (UCLASS_CLK). As a result - we don't need any other external list - it is just enough to look for UCLASS_CLK related udevices. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19dm: clk: Define clk_get_parent_rate() for clk operationsLukasz Majewski
This commit adds the clk_get_parent_rate() function, which is responsible for getting the rate of parent clock. Unfortunately, u-boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To alleviate this problem - the clk_get_parent_rate() function has been introduced to clk-uclass.c. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19dm: clk: Define clk_get_parent() for clk operationsLukasz Majewski
This commit adds the clk_get_parent() function, which is responsible for getting the parent's struct clock pointer. U-Boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To obtain the pointer to struct clk of parent the pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19clk: Provide struct clk for fixed rate clock (clk_fixed_rate.c)Lukasz Majewski
Up till now the fixed rate clock ('osc') has been added to UCLASS_CLK without declaring struct clk. As a result it was only accessible by iterating the udevice's uclass list. This is a problem for clock code, which operates on pointers to struct clk (like clk_get_rate()), not udevices. After this change struct clk is accessible from udevice and udevice from struct clk. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19clk: Remove clock ID check in .get_rate() of clk_fixed_*Lukasz Majewski
This check requires the struct clk passed to .get_rate() to be always cleared out as any clock with valid ID causes -EINVAL return value. The return code of fixed clocks shall always be returned. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19clk: sifive: Drop GEMGXL clock driverAnup Patel
The GEMGXL clock driver is now directly part of Cadence MACB ethernet driver in upstream Linux kernel. There is no separate GEMGXL clock driver in upstream Linux kernel hence we drop GEMGXL clock driver from U-Boot as well. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19clk: sifive: Sync-up main driver with upstream LinuxAnup Patel
The DT bindings of SiFive clock driver in upstream Linux has changes. As-per latest DT bindings, the clock driver takes two parent clocks and compatible string has also changed. This patch sync-up SiFive clock driver implementation as-per upstream Linux so that we now use latest DT bindings. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19clk: sifive: Sync-up DT bindings header with upstream LinuxAnup Patel
The location and license header of DT bindings header for SiFive clock driver has changed in upstream Linux hence this patch. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19clk: sifive: Sync-up WRPLL library with upstream LinuxAnup Patel
Now that SiFive clock driver is merged in upstream Linux, we sync-up WRPLL library used by SiFive clock driver with upstream Linux sources. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19clk: sifive: Factor-out PLL library as separate moduleAnup Patel
To match SiFive clock driver with latest Linux, we factor-out PLL library as separate module under drivers/clk/analogbits. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19clk: rockchip: rk3399: Fix check patch warnings and checksJagan Teki
- CHECK: spaces preferred around that '*' - CHECK: spaces preferred around that '/' - CHECK: space preferred before that '|' - WARNING: macros should not use a trailing semicolon - CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv' - CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC' - CHECK: Unnecessary parentheses around 'parent->dev == clk->dev' - WARNING: line over 80 characters - CHECK: Prefer kernel type 'u8' over 'uint8_t' - Add proper macro definitions arrangements Note: there are still line over 80 characters and other warnings but fixing those making code look unreadable, so I kept it as it is. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19rockchip: clk: rk3399: handle clk_enable requests for USB3Mark Kettenis
The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-16Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- Beelink-x2 STB support (Marcus) - H6 DDR3, LPDDR3 changes (Andre, Jernej) - H6 pin controller, USB PHY (Andre)
2019-07-16sunxi: clocks: Add H6 USB clock gates and resetsAndre Przywara
To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-14Merge tag 'u-boot-stm32-20190712' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - syscon: add support for power off - stm32mp1: add op-tee config - stm32mp1: add specific commands: stboard and stm32key - add stm32 mailbox driver - solve many stm32 warnings when building with W=1 - update stm32 gpio driver
2019-07-12clk: clk_stm32mp1: Fix warnings when compiling with W=1Patrick Delaunay
This patch solves the following warnings: drivers/clk/clk_stm32mp1.c: In function 'stm32mp1_clk_get_parent': warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++) ^ Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12stm32mp1: syscon: remove stgenPatrick Delaunay
Reduce difference with kernel Linux device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-10clk: uniphier: add EMMC clock for LD11, LD20, and PXs3Masahiro Yamada
I also added comments for NAND clocks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-11Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-bootTom Rini
- Add Ethernet support for STM32MP1 - Add saveenv support for STM32MP1 - Add STM32MP1 Avenger96 board support - Add SPI driver suport for STM32MP1 - Add watchdog support for STM32MP1 - Update power supply check via USB TYPE-C for STM32MP1 discovery board
2019-06-11clk: imx8qm: fix usdhc2 clocksMarcel Ziswiler
Trying to bring up uSDHC2 the following error message was observed: MMC: imx8_clk_set_rate(Invalid clk ID #60) imx8_clk_set_rate(Invalid clk ID #60) usdhc@5b030000 - probe failed: -22 This commit fixes this by properly setting resp. clocks. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-06-06stm32mp1: clk: use the correct identifier for ethckPatrick Delaunay
ETHCK_K is the identifier the kernel clock for ETH in kernel binding, selected by ETHKSELR / gated by ETHCKEN = BIT(7). U-Boot driver need to use the same identifier, so change ETHCK to ETHCK_K. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
2019-06-06clk: stm32mp1: Add SPI1 clock entryPatrice Chotard
Add missing SPI1 clock needed by SPI1 instance. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-06-01clk: sifive: Add clock driver for GEMGXL MGMTBin Meng
This adds a clock driver to support the GEMGXL management IP block found in FU540 SoCs to control GEM TX clock operation mode for 10/100/1000 Mbps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-05-31Merge tag 'rockchip-for-v2019.07-rc3' of git://git.denx.de/u-boot-rockchipTom Rini
- some fix for rk3399-puma; - rockchip script make_fit_atf.py cleanup - Enable TPL for rk3399 orangepi and nanopi4; - add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
2019-05-31clk: meson-g12a: Add PCIE PLL supportNeil Armstrong
The G12A PCIE PLL clock was introduced in Linux 5.2-rc1, and is needed for USB to operate, add basic support for it and associated gates. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-05-30rockchip: clk: rk3399: allow requests for all UART clocksChristoph Muellner
This patch adds the rate for UART1 and UART3 the same way as already implemented for UART0 and UART2. This is required for boards, which have their console output on these UARTs. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-23clk: stm32mp1: add set_rate for DDRPHYC clockPatrick Delaunay
Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-21mpc83xx_clk: Add enable methodMario Six
Some DM drivers have hardcoded clk_enable calls when handling clocks (for example the fsl_esdhc driver). To work with these drivers, add an enable method to the MCP83xx clock driver (which does nothing, because the clocks are always enabled). Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-09Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchipTom Rini
Improvements and new features: - split more rockchip pinctrl_core feature into per SoC - enable TPL for evb-rk3399 board - enable TPL/SPL for evb-px5 board - enable TPL and OP-TEE support for evb-rk3229 - update fix in arm common assembly start code for rockchip header file - update default SPL_FIT_GENERATOR for rockchip - rk3399 boards update to use '-u-boot.dtsi' - add new rk3399 boards: Nanopi M4, Nanopc T4 - enable sound for chromebook_minnie
2019-05-08Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
- H6 Beelink GS1 board (Clément) - Olimex A64-Teres-I board (Jonas) - sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej) - Change include order (Jagan) - EPHY clock changes (Jagan) - EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
2019-05-09clk: Use clk_get_by_index_tail()Jagan Teki
clk_get_by_index_tail() now handle common clk get by index code so use it from clk_get_by_indexed_prop(). Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09clk: Get the CLK by index without deviceJagan Teki
Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-09clk: sifive: fu540-prci: Change include orderJagan Teki
Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the fu540-prci driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from include/clk-uclass.h:13, from drivers/clk/sifive/fu540-prci.c:32: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in fu540-prci.c to include first common.h file. Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-08rockchip: clk: rk322x: fix assert clock valueKever Yang
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add CLK_EMMC_SAMPLE clock supportKever Yang
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-01Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchipTom Rini
Improvements and new features: - improved SPI driver for better read throughput - refactors initialisation of debug UART init - restructures header file paths - adds pinctrl improvements Adds Kever as a co-custodian.
generated by cgit (git 2.34.1) at 2024-12-29 15:12:44 +0000