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2019-05-21mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASEMario Six
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-03-03configs: fsl: move DDR specific defines to KconfigRajesh Bhagat
Moves below DDR specific defines to Kconfig: CONFIG_FSL_DDR_BIST CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE CONFIG_FSL_DDR_INTERACTIVE CONFIG_FSL_DDR_SYNC_REFRESH Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19drivers/ddr/fsl: Update fsl_ddr_board_options as weak functionPriyanka Jain
fsl_ddr_board_options is generally defined in board board's ddr.c, but some boards like lx2160ardb board does not need this function. Defining fsl_ddr_board_options as weak function to resolve compilation errors for such boards. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Fix checkpatch warnings] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2018-12-06armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-26drivers/ddr/fsl: fix '__hwconfig without a buffer' messagesJeremy Gebben
Pass an empty buffer instead of NULL if the hwconfig environment variable isn't set. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Cc: Stefano Babic <sbabic@denx.de> Cc: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-14Revert "drivers/ddr/fsl: Dual-license DDR driver"Tom Rini
Upon further review, not all code authors are in favour of this change. This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-09drivers/ddr/fsl: Dual-license DDR driverYork Sun
To make this driver easier to be reused, dual-license DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Simon Glass <sjg@chromium.org> CC: Tom Rini <trini@konsulko.com> CC: Heinrich Schuchardt <xypron.glpk@gmx.de> CC: Thomas Schaefer <thomas.schaefer@kontron.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Robert P. J. Day <rpjday@crashcourse.ca> CC: Alexander Merkle <alexander.merkle@lauterbach.com> CC: Joakim Tjernlund <joakim.tjernlund@transmode.se> CC: Curt Brune <curt@cumulusnetworks.com> CC: Valentin Longchamp <valentin.longchamp@keymile.com> CC: Wolfgang Denk <wd@denx.de> CC: Anatolij Gustschin <agust@denx.de> CC: Ira W. Snyder <iws@ovro.caltech.edu> CC: Marek Vasut <marek.vasut@gmail.com> CC: Kyle Moffett <Kyle.D.Moffett@boeing.com> CC: Sebastien Carlier <sebastien.carlier@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Peter Tyser <ptyser@xes-inc.com> CC: Paul Gortmaker <paul.gortmaker@windriver.com> CC: Peter Tyser <ptyser@xes-inc.com> CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2018-01-30drivers/ddr/fsl: Cleanup unused variableYork Sun
Variable "row_density" is no longer used. Drop it from DIMM structure. Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30drivers/ddr/fsl: Modify binding registers to save time on data initYork Sun
DDR controllers always use binding register to determine the memory space to perform data initialization. In case of controller interleaving, the space is doubled, resulting twice long wait. It wasn't too bad until the memory capacity increases. To reduce the wait time, reduce the binding space to half and restore it after data initialization. Three-way interleaving is no longer used and is removed. Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30drivers/ddr/fsl: Add calculation of register control wordsYork Sun
DDR4 RDIMM has some information in SPD to be used to calculate the control words for register chip. The rest can be found from JEDEC spec DDR4RCD02. Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30drivers/ddr/fsl: Add 3DS RDIMM supportYork Sun
On top of RDIMM support, add new register calculation to support 3DS RDIMMs. Only symmetrical 3DS is supported at this time. Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30drivers/ddr/fsl: Fix workaround for A009803York Sun
Wrong field was masked in this workaround due to wrong endianness. The impacted SoCs have big-endian. Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-30drivers/ddr/fsl: Fix DDR4 RDIMM supportYork Sun
For DDR4, command/address delay in mode registers and parity latency in timing config register are only needed for UDIMMs, but not RDIMMs. Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix calculation of timing config registers. Use hexadecimal format for printing RCW (register control word) registers. Signed-off-by: York Sun <york.sun@nxp.com>
2018-01-23ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCsRajesh Bhagat
Sets DDR configuration parameter cdr1 before all other settings to support case 0.9v VDD is enabled for some SoCs Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar
LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-16env: Rename getenv/_f() to env_get()Simon Glass
We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-12driver: ddr: fsl: Fix compiling error for DDR2York Sun
Fix compiling error of "no member named 'taamin_ps'" for DDR2. Signed-off-by: York Sun <york.sun@nxp.com>
2017-06-05common: arm: freescale: layerscape: Move header files out of common.hSimon Glass
We should not have an arch-specific header file in common.h. Adjust the board files a little so it is not needed, and drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05common: freescale: Move arch-specific declarationsSimon Glass
The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-18Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-04-18ddr: fsl: incorrect logical constraint in populate_memctl_optionsxypron.glpk@gmx.de
(pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40) is always true. We should use && here. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17drivers: ddr: fsl: fix unused-const-variable warningsThomas Schaefer
Depending on DDR configuration, gcc-6.x will show up unused-const- variable messages. Use __maybe_unused specifier for all dynamic_odt variable definitions to remove these warnings. Memory footprint will not increase as gcc will optimize out unused constants. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-13board_f: Rename initdram() to dram_init()Simon Glass
This allows us to use the same DRAM init function on all archs. Add a dummy function for arc, which does not use DRAM init here. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Dummy function on nios2] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05board_f: Drop return value from initdram()Simon Glass
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-01-04ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLSYork Sun
These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to KconfigYork Sun
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun
Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun
Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04fsl_ddr: Move DDR config options to driver KconfigYork Sun
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-05fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu
- add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-05fsl/ddr: Fix compiling warningShengzhou Liu
Fix following warning in case multiple erratum macro was not defined. warning: unused variable 'tmp' warning: unused variable 'ddr_freq' Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8555: Remove macro CONFIG_MPC8555York Sun
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: mpc8541: Remove macro CONFIG_MPC8541York Sun
Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-09-26Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-26driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun
Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-23drivers: squash lines for immediate returnMasahiro Yamada
Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-14ddr: fsl: fix a compile issueShaohui Xie
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that temp32 undeclared, this patch fixes it. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu
This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14driver/ddr/fsl: Revise workaround A008511 for A009803York Sun
DDR controller 5.2.1 has this erratum A008511 partially fixed. The workaround needs to be adjusted to take advantage of Vref training. This patch enables the training and force output enable to be off. Erratum A009803 requires the controller to be idel before enabling address parity. It was combined with workaround for A008511. With new A008511 flow, this flow needs to be changed to enabling data init (D_INIT) after the address parity is enabled. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-09-14driver/ddr/fsl: Add more debug registersYork Sun
32 more debug registers are added for newer DDR controllers. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-08-02driver/ddr/fsl: Fix timing_cfg_2York Sun
Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
2016-07-16Various, unrelated tree-wide typo fixes.Robert P. J. Day
Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2016-06-03driver/ddr/fsl: Check condition for erratum A-009803Shengzhou Liu
Add condition of checking the enabled of address parity for erratum A-009803, if parity is not enabled, the workaround of erratum A-009803 should not be applied. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03drivers/ddr/fsl: Disabling data init if ECC is not enabledYork Sun
If ECC is not enabled, data init can be disabled to speed up booting. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-03drivers/ddr/fsl: Fix timing_cfg_2 registerYork Sun
Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-03drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntlShengzhou Liu
The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series, but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs. We should update it to adapt the case that clk_adjust is odd data. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu
During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu
The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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