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path: root/drivers/ddr/fsl
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2017-06-05common: arm: freescale: layerscape: Move header files out of common.hSimon Glass
We should not have an arch-specific header file in common.h. Adjust the board files a little so it is not needed, and drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05common: freescale: Move arch-specific declarationsSimon Glass
The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-18Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-04-18ddr: fsl: incorrect logical constraint in populate_memctl_optionsxypron.glpk@gmx.de
(pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40) is always true. We should use && here. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17drivers: ddr: fsl: fix unused-const-variable warningsThomas Schaefer
Depending on DDR configuration, gcc-6.x will show up unused-const- variable messages. Use __maybe_unused specifier for all dynamic_odt variable definitions to remove these warnings. Memory footprint will not increase as gcc will optimize out unused constants. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-13board_f: Rename initdram() to dram_init()Simon Glass
This allows us to use the same DRAM init function on all archs. Add a dummy function for arc, which does not use DRAM init here. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Dummy function on nios2] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05board_f: Drop return value from initdram()Simon Glass
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-01-04ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLSYork Sun
These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to KconfigYork Sun
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun
Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun
Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04fsl_ddr: Move DDR config options to driver KconfigYork Sun
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-05fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu
- add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-05fsl/ddr: Fix compiling warningShengzhou Liu
Fix following warning in case multiple erratum macro was not defined. warning: unused variable 'tmp' warning: unused variable 'ddr_freq' Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8555: Remove macro CONFIG_MPC8555York Sun
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: mpc8541: Remove macro CONFIG_MPC8541York Sun
Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-09-26Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-26driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun
Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-23drivers: squash lines for immediate returnMasahiro Yamada
Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-14ddr: fsl: fix a compile issueShaohui Xie
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that temp32 undeclared, this patch fixes it. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu
This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14driver/ddr/fsl: Revise workaround A008511 for A009803York Sun
DDR controller 5.2.1 has this erratum A008511 partially fixed. The workaround needs to be adjusted to take advantage of Vref training. This patch enables the training and force output enable to be off. Erratum A009803 requires the controller to be idel before enabling address parity. It was combined with workaround for A008511. With new A008511 flow, this flow needs to be changed to enabling data init (D_INIT) after the address parity is enabled. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-09-14driver/ddr/fsl: Add more debug registersYork Sun
32 more debug registers are added for newer DDR controllers. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-08-02driver/ddr/fsl: Fix timing_cfg_2York Sun
Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
2016-07-16Various, unrelated tree-wide typo fixes.Robert P. J. Day
Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2016-06-03driver/ddr/fsl: Check condition for erratum A-009803Shengzhou Liu
Add condition of checking the enabled of address parity for erratum A-009803, if parity is not enabled, the workaround of erratum A-009803 should not be applied. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03drivers/ddr/fsl: Disabling data init if ECC is not enabledYork Sun
If ECC is not enabled, data init can be disabled to speed up booting. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-03drivers/ddr/fsl: Fix timing_cfg_2 registerYork Sun
Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-03drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntlShengzhou Liu
The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series, but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs. We should update it to adapt the case that clk_adjust is odd data. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu
During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu
The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17drivers/ddr/fsl: update workaround for erratum A-008511Shengzhou Liu
Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-27Fix typo choosen in comments and printf logsAlexander Merkle
Minor change: chosen is written with one "o". No code change here, only comment & printf. Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-21driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu
During initial DDR training, false parity errors may be detected. This patch adds workaround to fix the erratum. Tested on LS2085QDS and LS2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu
Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllersEd Swarthout
Following commit 61bd2f75, exclude unused DDR controller from calculating RAM size for SPL boot. Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25driver/ddr/fsl: Add workaround for A009663Shengzhou Liu
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu
During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-19Add more SPDX-License-Identifier tagsTom Rini
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-15move erratum a008336 and a008514 to soc specific fileYao Yuan
As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13driver/ddr/fsl: Update timing config for heavy loadYork Sun
In case four chip-selects are all active, the turnaround times need to increase to avoid overlapping under heavy load. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun
The workaround requires different setting for range 1 vs 2. Also adjust timeout value for waiting for controller to be idle. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13driver/ddr/fsl: Update MR5 RTT parkYork Sun
For four chip-selects enabled case, RTT is parked on all of them. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13driver/ddr/fsl: Update DDR4 MR6 for Vref rangeYork Sun
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13driver/ddr/fsl: Update DDR4 RTT valuesYork Sun
DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30drivers/ddr/fsl: Fix typo in BIST test for DDR4York Sun
BIST test code has a typo, resulting the binding registers not maintained as expected. This typo results BIST runs twice on the covered memory. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-11-30drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha
Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit (git 2.34.1) at 2024-12-27 17:09:14 +0000