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The mode argument of this function is not used at all, zap it.
Signed-off-by: Marek Vasut <marex@denx.de>
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Make this function more readable, no functional change. Also, zap the
forward declaration, which is no longer needed.
Signed-off-by: Marek Vasut <marex@denx.de>
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Implement universal scc_mgr_set_all_ranks() function and convert
various ad-hoc implementations of similar functionality to use
this single function. Document the function in kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
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Shuffle the code around a bit, but without any functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
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Clean up the comments and add kerneldoc. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
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Implement unified scc_mgr_set() function and convert all those
9 scc_mgr_set_*() ad-hoc functions to call this one function.
Signed-off-by: Marek Vasut <marex@denx.de>
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This patch just puts functions which look similar next to each
other, so they can be sorted out. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
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Clean up the unused args of the functions used to configure the
SCC manager.
Signed-off-by: Marek Vasut <marex@denx.de>
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Turn the insides of these functions into trivial clrsetbits_le32()
and fix the data type of their argument to reflect it's actual size.
Signed-off-by: Marek Vasut <marex@denx.de>
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Add brief kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
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Add brief kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
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Clean the function up, fix data types, add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
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Get rid of invocations of this sort:
addr = (u32)&base->reg;
writel(val, addr);
Signed-off-by: Marek Vasut <marex@denx.de>
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Use the proper structure which describes these registers,
especially since this is already in place.
Signed-off-by: Marek Vasut <marex@denx.de>
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Just trim down the constant SOCFPGA_SDR_ADDRESS + SDR_PHYGRP.*ADDRESS
in the code.
Signed-off-by: Marek Vasut <marex@denx.de>
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Remove the remaining invocations of sdr_get_addr() and the function
itself. This makes the code a bit less cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
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Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
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Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
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Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
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Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
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Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
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Use the correct formating string in those debug_cond() invocations
and zap those unnecessary ugly casts.
Signed-off-by: Marek Vasut <marex@denx.de>
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Fix the position of the } else { statement to make it correctly
indented.
Signed-off-by: Marek Vasut <marex@denx.de>
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The debug messages missed proper newlines and/or spaces in them.
Fix the formatting.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
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It is the configuration data that should go into the register,
not the register mask, just like the surrounding code does it.
Fix this typo.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
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Move the structure prototype from sdram.h header file into sdram.c
source file, since it is used only there and for local purpose only.
There is no point in having it global.
While at this move, fix the data types in the structure from uintNN_t
to uNN and fix the coding style a bit.
Signed-off-by: Marek Vasut <marex@denx.de>
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This file is absolutelly positively board specific, so move it
into the correct place.
Signed-off-by: Marek Vasut <marex@denx.de>
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This patch adds the DDR calibration portion of the Altera SDRAM driver.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.
Signed-off-by: York Sun <yorksun@freescale.com>
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Remove the incorrect PEX macros from the DDR header. And insert the
correct ones in ctrl_pex.h instead.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the Armada A38x boot image. Not linked with the main U-Boot. With this
code addition and the serdes/PHY setup code, the Armada A38x support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion.
Note:
This code has undergone many hours (days!) of coding-style cleanup and
refactoring. It still is not checkpatch clean though, I'm afraid. As the
factoring of the code has so many levels of indentation that many lines
are longer than 80 chars.
Signed-off-by: Stefan Roese <sr@denx.de>
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With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.
This will be the new structure:
drivers/ddr/marvell/axp
Supporting Armada XP (AXP) devices (and perhaps Armada 370)
drivers/ddr/marvell/a38x
Supporting Armada 38x devices (and perhaps Armada 39x)
Signed-off-by: Stefan Roese <sr@denx.de>
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In case SPD address changes between board revisions, updating SPD
address can be called from board file.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
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The macro to select the I2C address for ECC bus-width detection
was defined incorrectly for the Marvell DB-MV784MP-GP board. This
patch changes the macro to the correct value to fix this issue.
Signed-off-by: Stefan Roese <sr@denx.de>
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This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.
Signed-off-by: York Sun <yorksun@freescale.com>
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Add built-in memory test to catch errors after DDR is initialized, before
any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST.
An environmental variable "ddr_bist" is checked before starting test.
It takes a while (several seconds) depending on system memory size.
Signed-off-by: York Sun <yorksun@freescale.com>
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CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.
Signed-off-by: York Sun <yorksun@freescale.com>
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Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
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According to the MPC8555/MPC8541 reference manual the SS_EN (source
synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
during initialization.
>From section 9.4.1.8 of that manual:
Source synchronous enable. This bit field must be set during
initialization. See Section 9.6.1, "DDR SDRAM Initialization
Sequence," details.
0 - Reserved
1 - The address and command are sent to the DDR SDRAMs source
synchronously.
In addition, Freescale application note AN2805 is also very clear that
this bit must be set.
This patch reverts a change introduced by commit
457caecdbca3df21a93abff19eab12dbc61b7897.
Testing Done:
Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS
and inspected the generated assembly code to verify the SS_EN bit was being
set. There is one extra instruction emitted:
fff9b774: 65 29 80 00 oris r9,r9,32768
Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
additional instructions were emitted related to this patch.
Booted an image on a MPC8541 based board successfully.
Signed-off-by: Curt Brune <curt@cumulusnetworks.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.
Signed-off-by: York Sun <yorksun@freescale.com>
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wwt_bg should match rrt_bg. It was a typo in driver.
Signed-off-by: York Sun <yorksun@freescale.com>
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Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
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Erratum A008514 workround requires writing register eddrtqcr1 with
value 0x63b20002.
Signed-off-by: York Sun <yorksun@freescale.com>
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Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.
Signed-off-by: York Sun <yorksun@freescale.com>
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On ZeBu emulator, CAS to preamble overrides need to be set to
satisfy the timing. This only impact platforms with CONFIG_EMU.
These should be set before MEM_EN is set.
Signed-off-by: York Sun <yorksun@freescale.com>
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This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the AXP boot image. Not linked with the main U-Boot. With this code
addition and the following serdes/PHY setup code, the Armada-XP support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion. Hopefully other MVEBU SoC's will follow here.
Support for some SoC's has been removed in this version. This is:
MV_MSYS:
The code referred to by the MV_MSYS define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F68XX (A38x):
The code referred to by the MV88F68XX define (A38x) is currently unused.
And its partial and not sufficient for this device in this stage.
So lets remove it to make the code clearer and increase the readability.
MV88F66XX (ALP):
The code referred to by the MV88F66XX define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F78X60_Z1:
The code referred to by the MV88F78X60_Z1 define is currently unused. As the
Z1 revision of the AXP is not supported in mainline anymore.
So lets remove it to make the code clearer and increase the readability.
Remove support for Z1 & A0 AXP revisions (steppings). The current stepping
is B0 and this is the only one that is actively supported in this code
version.
Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and
on a custom fixed DDR configuration board (maxbcm).
Note:
This code has undergone many hours of coding-style cleanup and refactoring.
It still is not checkpatch clean though, I'm afraid. As the factoring of the
code has so many levels of indentation that many lines are longer than 80
chars. This might be some task to tackly later on.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
Signed-off-by: York Sun <yorksun@freescale.com>
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For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.
DDR4 is not affected by this change.
Signed-off-by: York Sun <yorksun@freescale.com>
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With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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