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2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27arm: socfpga: Fix with the correct polling on bit is setTien Fong Chee
Commit 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10") Polling on wrong cleared bit. Fix with correct polling on bit is set. Fixes: 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10") Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-04-09fpga: zynq: Add delay after PCFG_PROG_B changeSiva Durga Prasad Paladugu
There is delay needed after PCFG_PROGB change if AES key source is efuse. This fixes the issue of encrypted bitstream loading with AES efuse as key source. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09fpga: zynqmp: Fix the nonsecure bitstream loading issueSiva Durga Prasad Paladugu
Xilfpga library expects the size of bitstream in a pointer but currenly we are passing the size as a value. This patch fixes this issue. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09fpga: zynqmp: Update zynqmp_load() as per latest xilfpgaSiva Durga Prasad Paladugu
Latest xilfpga expects to set BIT5 of flags for nonsecure bitsream and also expects length in bytes instead of words This patch does the same. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-09fpga: zynqmp: Add support to get the PCAP status for fpga info commandNitin Jain
This patch adds support for ZynqMP platform to print FPGA PCAP status for "fpga status" command. Signed-off-by: Nitin Jain <nitinj@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23fpga: Simplify error path in fpga_addMichal Simek
Check !desc earlier to simplify code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-02-28arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPLVipul Kumar
This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2018-02-28fpga: Added Kconfig support for FPGA_SPARTAN3Vipul Kumar
This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas
wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-12-14fpga: allow programming fpga from FIT image for all FPGA driversGoldschmidt Simon
This drops the limit that fpga is only loaded from FIT images for Xilinx. This is done by moving the 'partial' check from 'common/image.c' to 'drivers/fpga/xilinx.c' (the only driver supporting partial images yet) and supplies a weak default implementation in 'drivers/fpga/fpga.c'. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Tested-by: Michal Simek <michal.simek@xilinx.com> (On zcu102) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-26arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytesTien Fong Chee
Existing FPGA program write is always assume RBF data >= 32 bytes, so any rbf data less than 32 bytes writing to FPGA would be failed. This patch enhances the FPGA program write to support rbf data with size >= 4 bytes. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2017-08-02fpga: xilinx: Avoid using local intermediate bufferSiva Durga Prasad Paladugu
Dont use local temporary buffer for printing out the info instead use directly from memroy. This fixes the issue of stack corruprion due to local buffer overflow. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-07-26arm: socfpga: Add FPGA driver support for Arria 10Tien Fong Chee
Add FPGA driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26kconfig: Convert FPGA_SOCFPGA configuration to KconfigTien Fong Chee
This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26arm: socfpga: Restructure FPGA driver in the preparation to support A10Tien Fong Chee
Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move FPGA manager driver from arch/arm into driver/fpga/. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-20fpga: zynqmppl: Reuse invoke_smc routineSiva Durga Prasad Paladugu
Reuse invoke_smc() routine which is already defined instead of duplicating same at multiple places. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-04-18FPGA: drivers/fpga/ivm_core.c: incorrect printfxypron.glpk@gmx.de
The number of arguments for printf does not match the format string. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-10fpga: zynqmp: Remove empty functionsMichal Simek
Xilinx core files will take care about it. There is no need to have these functions because they do nothing. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-12-16arm: imx: add i.MX53 Beckhoff CX9020 Embedded PCPatrick Bruenn
Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2016-09-23treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-22fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMPSiva Durga Prasad Paladugu
Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22fpga: Add Kconfig to fpga subsystemMichal Simek
Add missing Kconfig to fpga subsystem to be able to add new options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-07-16Various, unrelated tree-wide typo fixes.Robert P. J. Day
Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2016-05-24fpga: Fix typo in function commentMichal Simek
Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-03-24fpga: altera: Add StratixV supportStefan Roese
This patch adds support for programming of the StratixV FPGAs. Programming is done in this case (board theadorable) via SPI. The board may provide board specific code for bitstream programming. This StratixV support will be used by the theadorable board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-22Fix spelling of "transferred".Vagrant Cascadian
Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-04Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"Dinh Nguyen
Apparently, the logic for the FPGA global bit is not universal between Gen5 and Gen10 devices is not the same. Disabling this bit, while applicable to Gen10 devices, will break FPGA programming on Gen5 devices. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-01-27fpga: xilinx: Check for substring in device ID validationSiva Durga Prasad Paladugu
Check for substrings in deviceID validation check so that it can support xa bitstreams also. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-16arm: socfpga: set the fpga global bit to disable HPS to FPGA signalsDinh Nguyen
We should be setting the FPGA Interface Group global bit that will correctly disable all interfaces between the FPGA and HPS. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-11-19Move console definitions into a new console.h fileSimon Glass
The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-08arm: socfpga: Fix FPGA bitstream programming routineMarek Vasut
In case the FPGA bitstream is aligned to 4 bytes, skip the part of the assembler which handles unaligned bitstream. Otherwise, that part will loop indefinitelly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-01-21fpga: xilinx: Show fpga info if definedMichal Simek
Show fpga_op->info even if desc->iface_fns is not defined. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-21fpga: xilinx: Check if fpga operations are definedMichal Simek
Ensure that operations are correctly setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-21fpga: Export fpga_get_desc for SPLMichal Simek
SPL needs to detect FPGA device which will be used for loading bitstream. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-11-23fs: API changes enabling extra parameter to return size of type loff_tSuriyan Ramasami
The sandbox/ext4/fat/generic fs commands do not gracefully deal with files greater than 2GB. Negative values are returned in such cases. To handle this, the fs functions have been modified to take an additional parameter of type "* loff_t" which is then populated. The return value of the fs functions are used only for error conditions. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> [trini: Update board/gdsys/p1022/controlcenterd-id.c, drivers/fpga/zynqpl.c for changes] Signed-off-by: Tom Rini <trini@ti.com>
2014-10-06arm: socfpga: fpga: Add SoCFPGA FPGA programming interfacePavel Machek
Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support.
2014-10-06fpga: altera: Turn the switches into table lookupMarek Vasut
Add a table of FPGA family with matching functions associated with it and make all the code just look up the family in that table and call the associated function instead of the horrible switch voodoo which was duplicated all over the place. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06fpga: altera: Make altera_validate return normal valuesMarek Vasut
Make the function return either 0 or -EINVAL, that is, normal expected error codes and success codes instead of true/false nonsense. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06fpga: altera: Move altera_validate to the topMarek Vasut
Move the function to the top of the file to avoid forward declaration. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06fpga: altera: More indentation trimdownMarek Vasut
Further improve the indentation in the rest of the file, where the indentation is initially a bit less brutal. There is no functional change in this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06fpga: altera: Clean up altera_validate functionMarek Vasut
Boldly go, where no programmer has gone before and just clean up the indentation mayhem. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06fpga: altera: Clean up the printing and debugMarek Vasut
Clean up the printf() statements and get rid of the PRINTF() macro by replacing it with debug_cond(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-06-11m68k: Fix warnings with gcc 4.6Simon Glass
Most of the warnings seem to be related to using 'int' for size_t. Change this and fix up the remaining warnings and problems. For bootm, the warning was masked by others, and there is an actual bug in the code. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-05-20fpga: Added support to load bit stream from SD/MMCSiva Durga Prasad Paladugu
Added support to load a bitstream image in chunks by reading it in chunks from SD/MMC. Command format: loadfs [dev] [address] [image size] [blocksize] <interface> [<dev[:part]>] <filename> Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20fpga: zynqpl: Clean partial bitstream handlingMichal Simek
Do not do partial bitstream detection based on bitstream size and use bitstream_type argument which is passed from the fpga core. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20fpga: Define bitstream type based on command selectionMichal Simek
Clean up partial, full and compressed bitstream handling. U-Boot supports full bitstream loading and partial based on detection which is not 100% correct. Extending fpga_load/fpga_loadbitstream() with one more argument which stores bitstream type. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13fpga: zynq: Use helper function zynq_validate_bitstreamSiva Durga Prasad Paladugu
Use helper function zynq_validate_bitstream so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13fpga: zynq: Use helper functions for zynq dmaSiva Durga Prasad Paladugu
Use zynq_dma_xfer_init, zynq_align_dma_buffer, zynq_dma_transfer helper function performing dma transfers so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13fpga: zynq: Remove sparse warningsMichal Simek
Warnings: drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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