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path: root/drivers/i2c
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2014-09-24cosmetic: replace MIN, MAX with min, maxMasahiro Yamada
The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-24kconfig: add blank Kconfig filesMasahiro Yamada
This would be useful to start moving various config options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-09-08ls102xa: i2c: Add i2c support for LS102xAWang Huan
The existing i.MX's I2C driver mxc_i2c.c is compatible with the controller of LS102xA. As I2C's registers are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to use 8-bit driver. This patch is to add I2C 1,2,3 support for LS102xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-07-28Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-07-18sunxi: Add i2c supportHans de Goede
Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de> [ ijc -- updated u-boot-spl-fel.lds ]
2014-07-16mvtwsi: convert to CONFIG_SYS_I2C frameworkHans de Goede
Note this has only been tested on Allwinner sunxi devices (support for which gets introduced by a later patch). The kirkwood changes have been compile tested using the wireless_space board config, the orion5x changes have been compile tested using the edminiv2 board config. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Heiko Schocher <hs@denx.de>
2014-07-16fsl_i2c: add support for 3rd and 4th I2CShengzhou Liu
Add support for 3rd and 4th I2C. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-07-16i2c, omap24xx: add i2c deblock sequenzHeiko Schocher
If a bus busy is detected when intializing the driver, toggle 9 times the scl pin. Therefore enable the test mode of the controller, in which the scl, sda pins can be controlled manually. Tested on the siemens boards pxm2, rut and dxr2. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Lubomir Popov <lpopov@mm-sol.com> Cc: Steve Sakoman <steve@sakoman.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Vincent Stehlé <v-stehle@ti.com> Cc: Samuel Egli <samuel.egli@siemens.com>
2014-07-07board: gdsys: Make gdsys osd hardware detection more robustDirk Eibach
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2014-07-07i2c: IHS I2C master driverDirk Eibach
IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2014-07-07Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini
2014-07-03ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-07-03i2c: tegra: dump alen in debug statementsStephen Warren
Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
2014-07-03i2c: tegra: write clean data to TX FIFOStephen Warren
The Tegra I2C controller's TX FIFO contains 32-bit words. If the final FIFO entry of a transaction contains fewer than 4 bytes, the driver currently fills the unused FIFO bytes with uninitialized data. This can be confusing when reading back the FIFO content for debugging purposes. Solve this by explicitly initializing the variable containing FIFO data before filling it (partially) with data. With this change, send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e. read) branch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
2014-07-03i2c: tegra: use repeated start for readsStephen Warren
I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
2014-06-12i2c: kona: Resolve Kona I2C driver issueSteve Rae
- "i2c mw" command hangs (with some compilers) Signed-off-by: Steve Rae <srae@broadcom.com>
2014-05-14mvtwsi: Remove unnecessary twsi_baud_rate and twsi_slave_address globalsHans de Goede
These are used only once, so their is no need to have them global. This also stops mvtwsi from using any bss vars making it easier to use before dram init (to talk to the pmic to set the dram voltage). Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-05-14mvtwsi: Fix clock programmingHans de Goede
The TWSI_FREQUENCY macro was wrong in 2 ways: 1) It was casting the result of the calculations to an u8, while i2c clk rates are often >= 100Khz which won't fit in a u8, drop the cast. 2) It had an extra factor of 2 in the divider which neither the datasheet nor the Linux driver have. The comment for the default value was wrongly saying that m lives in bits 4-7, while in reality it is in bits 3-6, as can be seen from the correct shift by 3 used in i2c_init(). While at it remove the unused twsi_actual_speed variable. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-05-09Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-05-09Merge branch 'u-boot/master'Albert ARIBAUD
Conflicts: drivers/net/Makefile (trivial merge)
2014-05-08i2c: zynq: Fixed compilation errors when using DEBUGJesper B. Christensen
Signed-off-by: Jesper B. Christensen <jesper.christensen@cobham.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-04-29drivers/i2c/fsl_i2c: modify i2c_read to handle multi-byte writeShaveta Leekha
Most of the I2C slaves support accesses in the typical style that is : read/write series of bytes at particular address offset. These transactions look like:" (1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP" However there are certain devices which support accesses in terms of the transactions as follows: (2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching: RESTART:Address:Rx:data[0..n2]" Here Txdata is typically a command and some associated data, similarly Rxdata could be command status plus some data received as a response to the command sent. Type (1) transactions are currently supportd in the i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs, RTC, etc fall in this category. To handle type (2) along with type (1) transactions, i2c_read() function has been modified. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2014-04-29driver/mxc_i2c: Move static data structure to global_dataYork Sun
This driver needs a data structure in SRAM before SDRAM is available. This is not alway the case using .data section. Moving this data structure to global_data guarantees it is writable. Signed-off-by: York Sun <yorksun@freescale.com> CC: Troy Kisky <troy.kisky@boundarydevices.com>
2014-04-21Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-04-17i2c, davinci: convert driver to new mutlibus/mutliadapter frameworkVitaly Andrianov
- add davinci driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
2014-04-17i2c, davinci: move i2c_defs.h to the drivers/i2c directoryKaricheri, Muralidharan
This patch moves the davinci i2c_defs.h file to drivers.i2c directory. It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs. Not used "git mv" command to move the file because small part of it with definitions specific for Davinci SOCs has to remain in the arch/arm/include/asm/arch-davinci. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Tom Rini <trini@ti.com>
2014-04-14i2c: sh_i2c: bugfix: i2c probe command does not workTetsuyuki Kobayashi
This is regression of commit 2035d77d i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework Before commit 2035d77d, i2c probe command works properly on kzm9g board. KZM-A9-GT# i2c probe Valid chip addresses: 0C 12 1D 32 39 3D 40 60 After commit 2035d77d, i2c probe command does not work. KZM-A9-GT# i2c probe Valid chip addresses: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F sh_i2c_probe() calls sh_i2c_read(), but read length is 0. So acutally it does not read device at all. This patch prepares dummy buffer and read data into it. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-03-31drivers: i2c: delete an unused source fileMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de>
2014-02-26Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
Conflicts: arch/arm/cpu/armv7/config.mk board/ti/am43xx/mux.c include/configs/am43xx_evm.h Signed-off-by: Tom Rini <trini@ti.com>
2014-02-22i2c: kona: Add Kona I2C driverDarwin Rambo
Add support for the Kona I2C controller found on Broadcom mobile SoCs. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
2014-02-20Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-02-20designware_i2c: remove inclusion of <asm/arch/hardware.h>Alexey Brodkin
As soon as all boards have their CONFIG_SYS_I2C_BASE defined in configuration files instead of "asm/arch/hardware.h" it's safe to remove the inclusion in question and make driver platform-independent. Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Armando Visconti <armando.visconti@st.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2014-02-20OMAP24xx I2C: Add support for set-speedHannes Petermaier
Adds support for set-speed on the OMAP24xx I2C Adapter. Changes to omap24_i2c_write(...) for polling ARDY Bit from IRQ-Status. Otherwise on a subsequent call the transfer of last byte from the predecessor is aborted and therefore lost. For exmaple when i2c_write(...) is followed by a i2c_setspeed(...) (which has to deactivate and activate master for changing psc,...). Minor cosmetical changes. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Heiko Schocher <hs@denx.de>
2014-02-20i2c: i2c-mxs: Wait for I2C to empty queueMarek Vasut
Make sure the I2C write queue is empty before leaving the mxs_i2c_write(). If we start and I2C write and only wait for ACK, the MXS I2C IP block may enter next operation while still processing the write aftermath internally. This will in turn disrupt one or more subsequent transfer(s). A testcase for this issue is as such. This testcase is also interesting because the first I2C_WRITE which becomes disruptive happens in the 'i2c read' command. The 'i2c read' command first uses I2C_WRITE to send I2C address of the chip and then uses I2C_READ to read data from the chip. After this command completes, the 'i2c probe' will use sequence of I2C_WRITE commands to probe the I2C bus. The problem is that the first I2C_WRITE disrupted the I2C IP block operation and this sideeffect propagates all the way to this next I2C_WRITE used by the 'i2c probe' call. The result is the 'i2c probe' receives an ACK on I2C address 0x00, even if this ACK was owned by the previous I2C_WRITE operation. Note that the 'i2c read' command must read from a valid I2C chip address. Wrong: > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 00 50 51 With this patch > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 50 51 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
2014-02-20designware_i2c: Enhance DesignWare I2C driver address supportChin Liang See
Enhance the DesignWare I2C driver to support address length more than 1 byte. This enhancement is required as some I2C slave device such as EEPROM chip might have 16 bit address byte. Signed-off-by: Chin Liang See <clsee@altera.com> Acked-by: Alexey Brodkin <Alexey.Brodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> cc: Armando Visconti <armando.visconti@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de>
2014-02-20blackfin: make i2c driver blackfin independantScott Jiang
The ADI twi peripheral is not binding to Blackfin processor only. Access i2c registers by standard io functions. Fix coding style. Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-20blackfin: rename bfin-twi_i2c driver to adi_i2cSonic Zhang
The ADI twi peripheral is not binding to Blackfin processor only. Change to a generic name. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-20blackfin: add spi and i2c specific get clock functionsSonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-20blackfin: the sclk MHz in i2c driver should be divided by 1000 other than 1024Sonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-20i2c: zynq: Add support for the second i2c controllerMichael Burr
Initialize the second i2c controller. Signed-off-by: Michael Burr <michael.burr@logicpd.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-20i2c: zynq: Support for 0-length register addressMichael Burr
Fixed bug with alen == 0 in 'i2c_write', 'i2c_read' Further minor corrections: - Write 'address' register before 'data' register. - Write 'transfer_size' register before 'address' register. Signed-off-by: Michael Burr <michael.burr@logicpd.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-06ARM: IXP: Remove the IXP architecture supportMarek Vasut
The architecture is unmaintained and dead, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
2014-01-13i2c: fti2c010: fix compiler warning on paddr[]Kuo-Jung Su
This fixes the following compiler warnings: fti2c010.c: In function 'fti2c010_read': fti2c010.c:204:8: warning: 'paddr' may be used uninitialized in this function [-Wuninitialized] fti2c010.c: In function 'fti2c010_write': fti2c010.c:266:8: warning: 'paddr' may be used uninitialized in this function [-Wuninitialized] Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Heiko Schocher <hs@denx.de>
2014-01-13drivers/designware_i2c - add suppor of CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOWAlexey Brodkin
Since we agreed on legacy implementation of "eeprom_{read|write}" (http://patchwork.ozlabs.org/patch/295825/) I had to fix/make it work again DesignWare I2C driver for cases when 1 EEPROM IC fake I2C with anumber of "built-in" ICs with different chip addresses. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> cc: Armando Visconti <armando.visconti@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Vipin KUMAR <vipin.kumar@st.com> Cc: Tom Rix <Tom.Rix@windriver.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Kuo-Jung Su <dantesu@faraday-tech.com>
2014-01-13i2c: Fix i2c speed commandDarwin Rambo
This corrects i2c core to interpret the value returned by i2c_set_bus_speed as a success indicator rather than the actual speed that was set. When i2c_set_bus_speed returns a failure code, the speed is unknown so the adapter speed is set to zero. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Steve Rae <srae@broadcom.com> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-01-13rcar_i2c: Clear status before start master receiveNobuhiro Iwamatsu
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-01-13rcar_i2c: Fix receiving wait conditionHisashi Nakamura
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-12-18i2c: tegra: Add the fifth bus on SoC with more than 4 busesAlban Bedel
Create the i2c adapter object for the fifth bus on SoC with more than 4 buses. This allow using all the bus available on T30. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-10Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
Conflicts: board/samsung/trats2/trats2.c include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
2013-12-10Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD
Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
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