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path: root/drivers/mmc
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2018-02-19mmc: omap_hsmmc: Add support to set IODELAY valuesKishon Vijay Abraham I
The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. Add support to parse mux values and iodelay values from device tree and set these depending on the enumerated MMC mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: use mmc_of_parse to populate mmc_configKishon Vijay Abraham I
Use the mmc_of_parse library function to populate mmc_config instead of repeating the same code in host controller driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Reduce the max timeout for reset controller fsmJean-Jacques Hiblot
>From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines reset procedure section in TRM suggests to first poll the SRD/SRC bit until it is set to 0x1. But looks like that bit is never set to 1 and there is an observable delay of 1sec everytime the driver tries to reset DAT/CMD. (The same is observed in linux kernel). Reduce the time the driver waits for the controller to set the SRC/SRD bits to 1 so that there is no observable delay. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Workaround for errata id i802Jean-Jacques Hiblot
According to errata i802, DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure. The DCRC interrupt, occurs when the last tuning block fails (the last ratio tested). The delay from CRC check until the interrupt is asserted is bigger than the delay until assertion of the tuning end flag. Assertion of tuning end flag is what masks the interrupts. Because of this race, an erroneous DCRC interrupt occurs. The suggested workaround is to disable DCRC interrupts during the tuning procedure which is implemented here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Add tuning supportJean-Jacques Hiblot
HS200/SDR104 requires tuning command to be sent to the card. Use the mmc_send_tuning library function to send the tuning command and configure the internal DLL. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Enable DDR mode supportKishon Vijay Abraham I
In order to enable DDR mode, Dual Data Rate mode bit has to be set in MMCHS_CON register. Set it here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: set MMC mode in the UHSMS bit fieldJean-Jacques Hiblot
Use the timing parameter set in the MMC core to set the mode in UHSMS bit field. This is in preparation for adding HS200 support in omap hsmmc driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: add support to set default io voltageKishon Vijay Abraham I
"ti,dual-volt" is used in linux kernel to set the voltage capabilities. For host controller dt nodes that doesn't have "ti,dual-volt", it's assumed 1.8v is the io voltage. This is not always true (like in the case of beagle-x15 where the io lines are connected to 3.3v). Hence if "no-1-8-v" property is set, io voltage will be set to 3v. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: cleanup omap_hsmmc_set_iosKishon Vijay Abraham I
No functional change. Move bus width configuration setting to a separate function and invoke it only if there is a change in the bus width. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: cleanup clock configurationJean-Jacques Hiblot
Add a separate function for starting the clock, stopping the clock and setting the clock. Starting the clock and stopping the clock can be used irrespective of setting the clock (For example during iodelay recalibration). Also set the clock only if there is a change in frequency. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: use pr_* log functionsMasahiro Yamada
Use pr_* log functions from Linux. They can be enabled/disabled via CONFIG_LOGLEVEL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-02-08Move most CONFIG_HAVE_BLOCK_DEVICE to KconfigAdam Ford
config_fallbacks.h has some logic that sets HAVE_BLOCK_DEVICE based on a list of enabled options. Moving HAVE_BLOCK_DEVICE to Kconfig allows us to drastically shrink the logic in config_fallbacks.h Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rename HAVE_BLOCK_DEVICE to CONFIG_BLOCK_DEVICE] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-08Convert CONFIG_APBH_DMA et al to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_APBH_DMA CONFIG_APBH_DMA_BURST CONFIG_APBH_DMA_BURST8 Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Stefan Agner <stefan.agner@toradex.com> [trini: Add in MMC as well] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-04mmc: fsl_esdhc: support SDR104 and HS200Peng Fan
Introduce SDR104 and HS200 support The implementation takes linux kernel sdhci.c and sdhci-esdhc-imx.c as reference. - Implement esdhc_change_pinstate to dynamically change pad settings - Implement esdhc_set_timing - Implement esdhc_set_voltage to switch voltage - Implement fsl_esdhc_execute_tuning to execute time process - Enlarge the cfg->f_max to 200MHz. - Parse fsl,tuning-step, fsl,tuning-start-tap and fsl,strobe-dll-delay-target from device tree. - Parse no-1-8-v property - Introduce esdhc_soc_data to indicate the flags and caps Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-02-04mmc: fsl_esdhc: add strobe and tuning entryPeng Fan
Add entries that will be used for tuning control. The whole layout not changed, just expand reserved3[84] and rename other reservedx in sequence. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-02-04mmc: fsl_esdhc: support i.MX8MPeng Fan
Support i.MX8M in fsl esdhc driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-28mmc: Add bcm2835 sdhost controllerAlexander Graf
The BCM2835 family of SoCs has 2 different SD controllers: One based on the SDHCI spec and a custom, home-grown one. This patch implements a driver for the latter based on the Linux driver. This is needed so that we can make use of device trees that assume driver presence of both SD controllers. Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-26Merge git://git.denx.de/u-boot-spiTom Rini
2018-01-24mmc: Poll for broken card detection caseJun Nie
Poll for broken card detection case instead of return no card detected. Signed-off-by: Jun Nie <jun.nie@linaro.org>
2018-01-24mmc: fix to assign to correct clock value when clock is enablingJaehoon Chung
When clock is enabling, it's assigned to 0 as mmc->clock. Then it can't initialize any card. Fix to assign to correct clock value as mmc->cfg->f_min or f_max. Fixes: 9546eb92cb6 ("mmc: fix the wrong disabling clock") Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Guillaume GARDET <guillaume.gardet@free.fr> Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com>
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas
wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-22mmc: fsl_esdhc: Fix i.MX53 eSDHCv3 clockBenoît Thébaudeau
Commit 4f425280fa71 ("mmc: fsl_esdhc: Allow all supported prescaler values") made it possible to set SYSCTL.SDCLKFS to 0 in SDR mode on i.MX, thus bypassing the SD clock frequency prescaler, in order to be able to get higher SD clock frequencies in some contexts. However, that commit missed the fact that this value is illegal on the eSDHCv3 instance of the i.MX53. This seems to be the only exception on i.MX, this value being legal even for the eSDHCv2 instances of the i.MX53. Fix this issue by changing the minimum prescaler value for the single instance of the i.MX53 eSDHCv3 controller. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-22mmc: fix the wrong disabling clockJaehoon Chung
When power is off, clock is not disabling. Because it's passed to 1, mmc->clock should be set to f_min value. Some drivers can't initialize the eMMC/SD card with current status. This patch is to fix the disabling clock value to 0. Fixes: 2e7410d76ad1 ("mmc: disable the mmc clock during power off") Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Tested-by: Guillaume GARDET <guillaume.gardet@free.fr> Tested-by: Anand Moon <linux.amoon@gmail.com>
2018-01-22mmc: sdhci: change data transfer failure into debug messageMasahiro Yamada
During the tuning, drivers repeat data transfer, changing timing parameters in the controller hardware. So, the tuning commands (CMD19 for SD, CMD21 for eMMC) fail, and this is not a problem at all. Showing "Error detected..." in normal operation just make users upset. This should not be shown. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22mmc: sdhci-cadence: add HS200 supportMasahiro Yamada
Add HS200 timing setting and the MMC tuning callback. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-01-22mmc: sdhci-cadence: call mmc_of_parse()Masahiro Yamada
This is needed to parse more capabilities such as mmc-hs200-1_8v. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22mmc: sdhci-cadence: use bitfield access macros for cleanupMasahiro Yamada
This driver is a counterpart from the one in Linux. Follow the clean-up I did in Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22mmc: sdhci: do not overwrite host_caps in sdhci_setup_cfg()Masahiro Yamada
This line overwrites host_cap that has been set by drivers and/or helpers like mmc_of_parse(). Accumulate capabilities flags. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22mmc: let mmc_of_parse() fail for insane bus-width valueMasahiro Yamada
You must fix your DT if it specifies insane bus-width, for example, bus-width = <3>; debug() is not displayed in usual configuration, so people will not even notice weirdness. Use dev_err() instead, then let it fail. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22mmc: do not overwrite cfg->f_max if "max-frequency" if missingMasahiro Yamada
mmc_of_parse() in U-Boot is a pussy helper; it sets cfg->f_max to 52MHz even if DT does not provide "max-frequency" at all. This can overwrite cfg->f_max that may have been set to a reasonable default. As the DT binding says, "max-frequency" is an optional property. Do nothing if DT does not specify it. This is the behavior of mmc_of_parse() in Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-19mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bitKishon Vijay Abraham I
omap_hsmmc driver uses "|" in a couple of places for disabling a bit. While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a _mask_ argument to take care of resetting a bit), it's incorrectly used for resetting flags in "omap_hsmmc_send_cmd". Fix it here by using "&= ~()" to reset a bit. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19mmc: omap_hsmmc: Enable Auto command (CMD12) enableKishon Vijay Abraham I
Instead of sending STOP TRANSMISSION command from MMC core, enable the auto command feature so that the Host Controller issues CMD12 automatically when last block transfer is completed. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19mmc: omap_hsmmc: Add support for DMA (ADMA2)Kishon Vijay Abraham I
The omap hsmmc host controller can have the ADMA2 feature. It brings better read and write throughput. On most SOC, the capability is read from the hl_hwinfo register. On OMAP3, DMA support is compiled out. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-18Revert "omap_hsmmc: update struct hsmmc to accommodate omap3 from DT"Jean-Jacques Hiblot
This reverts commit 46831c1a4cda75d92f7ad18d4e2b1eb196c62b2f. This reserved area at the beginning of struct hsmm, will be used later to support ADMA Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-13mmc: fsl_esdhc: Fix eMMC 1.8v setting issuePeng Fan
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init, then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has already set VSELECT to 1.8v before running the u-boot. This reset in USDHC driver causes a short 2.2v pulse on CMD pin. Fix this issue by not reset VSELECT to 0 when 1.8v flag is set. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12mmc: remove hc_wp_grp_size from struct mmc if not neededJean-Jacques Hiblot
hc_wp_grp_size is needed only if hardware partitionning is used. On ARM removing it saves about 30 bytes of code space. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: don't read the size of eMMC enhanced user data area in SPLJean-Jacques Hiblot
This information is only used by the "mmc info" command. On ARM removing this information from SPL saves about 140 of code space. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: compile out erase and write mmc commands if write operations are not ↵Jean-Jacques Hiblot
enabled Also remove erase_grp_size and write_bl_len from struct mmc as they are not used anymore. On ARM, removing them saves about 100 bytes of code space in SPL. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: read ssr only if MMC write support is enabledJean-Jacques Hiblot
The content of ssr is useful only for erase operations. on ARM, removing sd_read_ssr() saves around 300 bytes. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: add a Kconfig option to enable the support for MMC write operationsJean-Jacques Hiblot
This allows using CONFIG_IS_ENABLED(MMC_WRITE) to compile out code needed only if write support is required. The option is added for u-boot and for SPL Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: reworked version lookup in mmc_startup_v4Jean-Jacques Hiblot
Using a table versus a switch() structure saves a bit of space Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: compile out more code if support for UHS and HS200 is not enabledJean-Jacques Hiblot
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: atmel: when sending a data command, use the provided block sizeJean-Jacques Hiblot
struct mmc_data contains the block size to use for the data transfer. Use this information instead of using the default value or the block length information stored in struct mmc. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12dm: mmc: sandbox: Update SD card emulationJean-Jacques Hiblot
The SDcard initialization procedure does a few more things than it did earlier: * switch the bus width even for 1-bit bus width * check that speed has been properly set (in resp[4] of SD_CMD_SWITCH_FUNC) Update the SD simulator to handle those requests gracefully. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-01-12mmc: make optional the support for eMMC hardware partitioningJean-Jacques Hiblot
Not all boards have an eMMC and not all users have a need for this. Allow to compile it out. By default it is still included. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: make UHS and HS200 optionalJean-Jacques Hiblot
Supporting USH and HS200 increases the code size as it brings in IO voltage control, tuning and fatter data structures. Use Kconfig configuration to select which of those features should be built in. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: convert most of printf() to pr_err() and pr_warn()Jean-Jacques Hiblot
This allows to compile out the log message by tweaking the LOGLEVEL. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-12mmc: don't use malloc_cache_aligned()Jean-Jacques Hiblot
Not using this function reduces the size of the binary. It's replaces by a standard malloc() and the alignment requirement is handled by an intermediate buffer on the stack. Also make sure that the allocated buffer is freed in case of error. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: fix for old MMCs (below version 4)Jean-Jacques Hiblot
The ext_csd is allocated only for MMC above version 4. The compare will crash or fail for older MMCs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: all hosts support 1-bit bus width and legacy timingsJean-Jacques Hiblot
Make sure that those basic capabilities are advertised by the host. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
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