| Age | Commit message (Collapse) | Author |
|---|
|
This patch adds esdhc support for ls2085a.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
|
|
Move arch/arm/include/asm/arch-bcm283x/*
-> arch/arm/mach-bcm283x/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
|
|
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
SDHCI_HOST_CONTROL is a byte-sized register, so don't write to it
as if it were a long, as that would result in clobbering the three
registers following.
Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
|
|
Properly mask SELBASECLK by using an actual mask rather than the
number of bits to shift in order to create the mask.
Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
|
|
Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces
error register offset.
Change the "char reserved3[59]" to "char reserved3[56]".
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
|
|
|
|
Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.
Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
|
Fix bus width switching from 8-bit mode down to 4-bit or 1-bit modes on
Samsung SoCs using SDHCI_QUIRK_USE_WIDE8. These SoCs report controller
version 2.0 yet they support 8-bit bus widths. If 8-bit mode was
previously enabled and then an operation like "mmc dev" caused a switch
back down to 4-bit or 1-bit mode, WIDE8 was left set, causing failures.
This problem was manifested by "mmc dev" timing out.
Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
|
|
Depending on the boot priority, the eMMC/SD cards,
can be initialized with the same numbers for each boot.
To be sure which mmc device is SD and which is eMMC,
this info is printed by 'mmc list' command, when
the init is done.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1, etc.
In case of possibility to boot from more then one device,
the CONFIG_SYS_MMC_ENV_DEV should always point to right mmc device.
This can be achieved by init boot device as first, so it will be
always registered as mmc 0. Thanks to this, the 'saveenv' command
will work fine for all mmc boot devices.
Exynos based boards usually uses mmc host channels configuration:
- 0, or 0+1 for 8 bit - as a default boot device (usually eMMC)
- 2 for 4bit - as an optional boot device (usually SD card slot)
And usually the boot order is defined by OM pin configuration,
which can be changed in a few ways, eg.
- Odroid U3 - eMMC card insertion -> first boot from eMMC
- Odroid X2/XU3 - boot priority jumper
By this commit, Exynos dwmmc driver will check the OM pin configuration,
and then try to init the boot device and register it as mmc 0.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Akshay Saraswat <akshay.s@samsung.com>
|
|
High Capacity (e)MMC cards work fine on sun4i / sun5i, and not having this
capability set causes u-boot to not recognize the eMMC on an Utoo P66 A13
tablet, so always set it thereby fixing this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
Clksel value is exynos specific value.
It removed "clksel_val" into dwmci_host and created the
"dwmci_exynos_priv_data" structure for exynos specific data.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
|
|
"clksel_val" is assigned to property of mmc or defined value.
But it doesn't write at initial sequence.
There is a reason that get the wrong source-clock value.
This patch fixed it.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
|
|
If mode is not DDR-mode, then it needs to clear it.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
|
|
Some boards cannot do voltage negotiation but need to set the VSELECT
bit forcely to ensure it to work at 1.8V.
This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
|
|
This adds support to switch to 1.8V in case CMD11 succeeds.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Marek Vasut <marex@denx.de>
|
|
Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.
This creates a generic PCI MMC device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
|
|
|
|
|
This results in a much more readable callgraph, because now they
can't be confused with the function having exactly the same name
in the generic mmc code.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
|
These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
|
|
|
|
The clocks on the A80 are hooked up slightly different, add support for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
Wait 1 second for the sdcard to respond, rather then waiting for
0xfffff milliseconds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
phys_addr_t is designed for physical addresses that's why
use it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Wider bus widths (larger than default 1 bit) appeared in MMC standard
version 4.0. So, for MMC cards of any earlier version trying to change
the bus width (including ext_csd comparison) does not make any sense.
It may work incorrectly and at least cause unnecessary timeouts.
So, just skip the entire bus width related activity for earlier versions.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Tested-by: Alexey Brodkin <abrodkin@synopsys.com>
|
|
If all the commands switching an MMC card to 4- or 8-bit bus width fail,
and the bus width for the controller and the driver is still set
to default 1 bit, there is no need to send one more command to switch
the card to 1-bit bus width. Also, if the card or host controller do not
support wider bus widths, there is no need to send a switch command at all.
However, if one of switch commands succeeds, but the subsequent ext_csd
fields comparison fails, the card should be switched to some other bus width
(next in the list for the loop), or to default 1-bit bus width as a last
resort. That's why it would be incorrect to just remove the 1-bit bus width
case from the list, it should still be processed in some cases.
panto: Minor cosmetic edit removing superfluous parentheses.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Tested-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
|
|
This extends the mmcinfo hardware partition info output to show
partitions with write reliability enabled with the "WRREL" string.
If the partition does not have write reliability enabled the "WRREL"
string is omitted; this is analogous to the ehhanced attribute.
Example output:
Device: OMAP SD/MMC
Manufacturer ID: fe
OEM: 14e
Name: MMC16
Tran Speed: 52000000
Rd Block Len: 512
MMC version 4.41
High Capacity: Yes
Capacity: 13.8 GiB
Bus Width: 4-bit
Erase Group Size: 8 MiB
HC WP Group Size: 16 MiB
User Capacity: 13.8 GiB ENH WRREL
User Enhanced Start: 0 Bytes
User Enhanced Size: 512 MiB
Boot Capacity: 16 MiB ENH
RPMB Capacity: 128 KiB ENH
GP1 Capacity: 64 MiB ENH WRREL
GP2 Capacity: 64 MiB ENH WRREL
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
The eMMC partition write reliability settings are to be set while
partitioning a device, as per the eMMC spec, so changes to these
attributes needs to be done in the hardware partitioning API.
This commit adds such support.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
This adds an API to do hardware partitioning on eMMC devices. The
new mmc_hwpart_config() function does the partitioning in one go.
As the different attributes and partitioning options on eMMC may
be interdependent validation has to be done based on the complete
partitioning configuration. The function accepts three modes:
- MMC_HWPART_CONF_CHECK: just validates that the configuration
is valid.
- MMC_HWPART_CONF_SET: validates and sets all the fields in
EXT_CSD but without setting the "partitioning completed" bit,
and thus is reversible.
- MMC_HWPART_CONF_COMPLETE: does everything and is thus not
reversible.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
The mmc_startup() function uses the ext_csd data even if reading it
from the mmc device failed. This bug was introduced in commit
bc897b1d4d86597311430dbe7b3e6c807c8c53e5. We now bail out if
reading it fails, this should not be a problem as ext_csd was
introduced in MMC 4.0 and this code is conditional on MMC >= 4.0.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
The eMMC spec says that partitioning is only effective after the
PARTITION_SETTING_COMPLETED is set in EXT_CSD (and a power cycle was done,
but that we cannot know). Thus the partition sizes and attributes should
be ignored when that bit is not set, otherwise the various capacities
are not coherent (e.g., the user data capacity will be that of the
unpartitioned device while partition sizes would be non-zero).
Prescence of non-zero partitioning data is nevertheless still used to
activate the high-capacity size definitions (EXT_CSD_ERASE_GROUP_DEF)
as it is necessary to set that to write any of the partitioning fields
in EXT_CSD, so having partitioning data means someone previously
activated that and we should keep it activated.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
Read the eMMC high capacity write protect group size at mmc device
initialization. This is useful to correctly partition an eMMC device,
as partitions need to be aligned to this size.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
The erase_grp_size in struct mmc is to be a size in 512-byte sectors
but the code used to compute it for eMMC when EXT_CSD_ERASE_GROUP_DEF is
enabled computed it as bytes, leading to erase sizes and alignment
much larger than what is actually required by the mmc device.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
This modification reads the size of the eMMC enhanced user data area
upon initialization of an mmc device, it will be used later by
mmcinfo.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
The eMMC spec mandates that the high-capacity group size definitions
should be enabled when the device is partitioned (by setting
ERASE_GROUP_DEF in EXT_CSD). The current test to determine when this is
required misses a few cases. In particular a device may have been
partitioned without setting the enhanced attribute on any partition
or partitioning may be completed without creating any extra partitions.
This change moves the code to set ERASE_GROUP_DEF to after reading
all partition information. It is also enabled when
PARTITIONING_SETTING_COMPLETED is set as it is necessary to enable
ERASE_GROUP_DEF before setting that bit, so it means that the user
previously switched to the high capacity definitions.
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
This extends the mmcinfo command's output to show which eMMC partitions
have the enhanced attribute set. Note that the eMMC spec says that
if the enhanced attribute is supported then the boot and RPMB
partitions are of the enhanced type.
The output of mmcinfo becomes:
Device: OMAP SD/MMC
Manufacturer ID: fe
OEM: 14e
Name: MMC16
Tran Speed: 52000000
Rd Block Len: 512
MMC version 4.41
High Capacity: Yes
Capacity: 13.8 GiB
Bus Width: 4-bit
User Capacity: 13.8 GiB ENH
Boot Capacity: 16 MiB ENH
RPMB Capacity: 128 KiB ENH
GP1 Capacity: 64 MiB ENH
GP2 Capacity: 64 MiB ENH
Signed-off-by: Diego Santa Cruz <Diego.SantaCruz@spinetix.com>
|
|
This adds Renesas rmobile ARM SoC's SD/MMC host support.
This drivers tested with Gose board and Koelsch board.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
It does not make sense to make gpio_direction_input() return the gpio input
status. The return value of gpio_direction_input() is inconsistent if
CONFIG_DM_GPIO is defined.
And we don't need to call gpio_direction_input() int sunxi_mmc_getcd().
Just init the gpio once in mmc_resource_init() is enough.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
|
|
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.
The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).
For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.
This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
Remove unnessecary delay from mvebu_mmc_initialize
Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
Clean mvebu_mmc_send_cmd
Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
Remove delays in mvebu_mmc_set_bus and mvebu_mmc_set_clk
Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
Get about 40x faster access on SHEEVAPLUG MMC
Fix some SD type compatibility
Changes in v3:
- fix the HW_STATE (from linux mvsdio)
- review delays and timeouts
Changes in v2:
- increase number of loops
- remove initial delay
Changes in v1:
- review all loops, delays and timeouts
Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
|
|
Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
|
