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path: root/drivers/mtd/nand/fsl_ifc_nand.c
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2016-09-23treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-06-03mtd: nand: Add page argument to write_page() etc.Scott Wood
This change is part of the Linux 4.6 sync. It is being done before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_dataScott Wood
These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03nand: Embed mtd_info in struct nand_chipScott Wood
nand_info[] is now an array of pointers, with the actual mtd_info instance embedded in struct nand_chip. This is in preparation for syncing the NAND code with Linux 4.6, which makes the same change to struct nand_chip. It's in a separate commit due to the large amount of changes required to accommodate the change to nand_info[]. Signed-off-by: Scott Wood <oss@buserror.net>
2015-08-25nand: Sync with Linux v4.1Scott Wood
Update the NAND code to match Linux v4.1. The previous sync was from Linux v3.15 in commit 4e67c57125290b25. CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now has its own timeout. Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented and not selected by any board. Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-04-23driver/ifc: Add 64KB page supportJaiprakash Singh
IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23nand/fsl_ifc: Increase eccstat[] for IFC 2.0Scott Wood
IFC 2.0 doubled the SRAM size, which means double the number of ECCSTAT registers. Fix the resulting array overflow. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-30nand: Remove CONFIG_MTD_NAND_VERIFY_WRITEPeter Tyser
The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some time and a more generic method of NAND verification now exists in U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
2014-12-11driver/mtd: Fix IFC compilation warningsJaiprakash Singh
'eccstat' array elements might be used uninitialized Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-25driver/mtd: Use generic timer API for FSL IFC, eLBCPrabhakar Kushwaha
Freescale's flash control driver is using architecture specific timer API i.e. usec2ticks Replace usec2ticks with get_timer() (generic timer API) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-25mtd, ubi, ubifs: resync with Linux-3.14Heiko Schocher
resync ubi subsystem with linux: commit 455c6fdbd219161bd09b1165f11699d6d73de11c Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Mar 30 20:40:15 2014 -0700 Linux 3.14 A nice side effect of this, is we introduce UBI Fastmap support to U-Boot. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Sergey Lapin <slapin@ossfans.org> Cc: Scott Wood <scottwood@freescale.com> Cc: Joerg Krause <jkrause@posteo.de>
2014-07-22driver/nand: Add support of 16K SRAM for IFC 2.0Prabhakar Kushwaha
Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0. Update the page offset calculation logic to support the same. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22driver/nand: Update SRAM initialize logic for IFC.Prabhakar Kushwaha
IFC controller v1.1.0 requires internal SRAM initialize by reading NAND flash. Higher controller versions have provided "SRAM init" bit in NCFGR register space. update SRAM initialize logic to reflect the same. Also print error message in case of Page read error. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22driver/nand:Define MAX_BANKS same as SoC defined for IFCPrabhakar Kushwaha
The number of chip select used by IFC controller vary from one SoC to other. For eg. P1010 has 4, T4240 has 8. Update MAX_BANKS same as SoC defined Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-03driver/ifc:Change accessor function to take care of endiannessPrabhakar Kushwaha
IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
2013-12-02Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini
2013-11-25Driver/IFC: Move Freescale IFC driver to a common driverYork Sun
Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-21mtd/ifc: Add support of 8K page size NAND flashPrabhakar Kushwaha
Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
2013-11-13driver/mtd/ifc: Read Status while programming NAND flashPrabhakar Kushwaha
as per controller description, "While programming a NAND flash, status read should never skipped. Because it may happen that a new command is issued to the NAND Flash, even when the device has not yet finished processing the previous request. This may result in unpredictable behaviour." IFC controller never polls for R/B signal after command send. It just return control to software. This behaviour may not occur with NAND flash access. because new commands are sent after polling R/B signal. But it may happen in scenario where GPCM-ASIC and NAND flash device are working simultaneously. Update the controller driver to take care of this requirement Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-05-31mtd: resync with Linux-3.7.1Sergey Lapin
This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: Sergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-05-22nand/fsl_ifc: Convert to self-initPrabhakar Kushwaha
Convert NAND IFC driver to support CONFIG_SYS_NAND_SELF_INIT. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-12-21driver/mtd/IFC:Wait tWB time, poll R/B before command executionPrabhakar Kushwaha
IFC_FIR_OP_CMD0 issues command for execution without checking flash readiness. It may cause problem if flash is not ready. Instead use IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or time-out, before issuing command. NAND_CMD_READID command implemention does not fulfill above requirement. So update its programming. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Hemant Nautiyal <hemant.nautiyal@freescale.com>
2012-11-26driver/mtd:IFC NAND:Initialise internal SRAM before any writePrabhakar Kushwaha
IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for SRAM i.e. "byte select" is not supported. Hence Read Modify Write is implemented in IFC for any "system side write" into sram buffer. Reading an uninitialized memory results in ECC Error from sram wrapper. Hence we must initialize/prefill SRAM buffer by any data before writing anything in SRAM from system side. To initialize SRAM user can use "READID" NAND command with read bytes equal to SRAM size. It will be a one time activity post boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [scottwood@freescale.com: fix fsl_ifc_sram_init prototype] Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-11-26nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC driversScott Wood
These controllers can only do hardware ECC on full page transfers. Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-05-18driver/mtd:IFC: Fix possible memory leakPrabhakar Kushwaha
if priv->bank >= MAX_BANK, priv should be freed before returning ENODEV. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scott@tyr.buserror.net>
2012-05-18driver/mtd: IFC NAND: Add support of ONFI NAND flashPrabhakar Kushwaha
- Fix NAND_CMD_READID command for ONFI detect. - Add NAND_CMD_PARAM command to read the ONFI parameter page. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scott@tyr.buserror.net>
2012-02-28mtd/nand:Fix wrong usage of is_blank() in fsl_ifc_run_commandPrabhakar Kushwaha
Freescale IFC NAND Machine calculates ECC on 512byte sector and same is used in fsl_ifc_run_command() during ECC status verification. Also this sector is passed to is_blank() for blank checking. It is wrong at first place because is_blank()'s implementation checks for Page size and OOB area size. is_blank() should be called per page for main and OOB area verification. Variables name are redefined to avoid confusion between buffer and ecc sector. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-02-28mtd/nand: Fix IFC driver to support 2K NAND pagePrabhakar Kushwaha
1) OOB area should be updated irrespective of NAND page size. Earlier it was updated only for 512byte NAND page. 2) During OOB update fbcr should be equal to OOB size. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-09-29nand: Freescale Integrated Flash Controller NAND supportDipen Dudhat
Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
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