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path: root/drivers/mtd/nand
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2018-06-27mtd: nand: mxs_nand: add device tree supportStefan Agner
Support driver data from device tree. Also support fsl,use-minimal-ecc similar to Linux' GPMI NAND driver. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: move structs into header fileStefan Agner
Move structs into header file so we can use a separate compile unit for device tree support. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: add use_minimum_ecc to structStefan Agner
Add use_minimum_ecc as struct mxs_nand_info field in preparation for device tree support. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: separate board/controller initStefan Agner
In preparation for device tree support separate board init from controller init similar to other raw NAND drivers. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: use more precise function nameStefan Agner
This function initializes DMA descriptors so mxs_nand_init_dma is more precise. It also frees up the rather generic name mxs_nand_init. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: move register structs to driver dataStefan Agner
Move GPMI and BCH register structs to the driver struct mxs_nand_info in prepartion for device tree support. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: add minimal ECC supportStefan Agner
Add support for minimum ECC strength supported by the NAND chip. This aligns with the behavior when using the fsl,use-minimum-ecc device tree property in Linux. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: report correct ECC parametersStefan Agner
Report correct ECC parameters back to the stack. Do not report bytes as we have it not immeaditly available and the Linux version also does not report it. It seems to have no aversive effect. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: use structure for BCH geometryStefan Agner
Calculate BCH geometry at start and store the information in a structure. This avoids recalculation on every page access and allows to calculate ECC relevant information in one place. This patch does not change ECC layout or driver behavior in any way. The patch aligns the driver somewhat with the Linux GPMI NAND driver which drives the same IP. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: allow to enable BBT supportStefan Agner
Add config option which allows to enable on flash bad block table support. This has the same effect as when using the device tree property "nand-on-flash-bbt" in Linux. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: use self initStefan Agner
Instead of completing initialization via scan_bbt callback use NAND self init to initialize the GPMI (MXS) NAND controller. Suggested-by: Scott Wood <oss@buserror.net> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: introduce SPL specific initStefan Agner
In preparation to convert the driver to use NAND self init provide a new minimal init for SPL builds. As a side effect this also reduces size of SPL by about 4KiB. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-05-11Merge git://git.denx.de/u-boot-tegraTom Rini
2018-05-11Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup
2018-05-11nand: zynq: Send address cycles as per onfi parameter pageSiva Durga Prasad Paladugu
Send address cycles as per value read from onfi parameter page for Read and write commands instead of using a hard coded value. This may vary for different parts and hence use it from onfi parameter page value. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11nand: zynq: Add support for 16-bit buswidthSiva Durga Prasad Paladugu
This patch adds support for 16-bit buswidth by determining the bus width based on mio configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-10mtd: nand: tegra: convert to driver model and live treeMarcel Ziswiler
The Tegra NAND driver recently got broken by ongoing driver model resp. live tree migration work: NAND: Could not decode nand-flash in device tree Tegra NAND init failed 0 MiB A patch for NAND uclass support was proposed about a year ago: https://patchwork.ozlabs.org/patch/722282/ It was not merged and I do not see on-going work for this. This commit just provides a driver model probe hook to retrieve further configuration from the live device tree. As there is no NAND ulass as of yet (ab)using UCLASS_MTD. Once UCLASS_NAND is supported, it would be possible to migrate to it. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-05-09mtd: nand: fsl_ifc: Fix nand waitfunc return valueJagdish Gediya
As per the IFC hardware manual, Most significant byte in nand_fsr register is the outcome of NAND READ STATUS command. So status value need to be shifted as per the nand framework requirement. Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09mtd: nand: fsl_ifc: Fix eccstat array overflow for IFC ver >= 2.0.0Jagdish Gediya
Number of ECC status registers i.e. (ECCSTATx) has been increased in IFC version 2.0.0 due to increase in SRAM size. This is causing eccstat array to over flow. So, replace eccstat array with u32 variable to make it fail-safe and independent of number of ECC status registers or SRAM size. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-23nand: zynq: Cleanup initializationEzequiel Garcia
CONFIG_NAND_ZYNQ selects CONFIG_SYS_NAND_SELF_INIT, so the driver doesn't have to play any ifdef game. Also, we can mark zynq_nand_init() as static and get rid of the mach-specific nand.h header. This is really a revert of: "mtd: zynq: nand: Move board_nand_init() function to board.c" (sha1: 310995d9f91ae56082b49be06fe8c3d01424f8f6) Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23nand: zynq: Fix driver initializationEzequiel Garcia
This driver is currently broken, refusing to initialize properly. The reason is that get_nand_dev_by_index() was being called before nand_register(), thus returning a pointer into uninitialized memory. In other words, the struct mtd_info used by the driver is total junk. Fix it by getting the correct struct mtd_info, via nand_to_mtd() on the driver's struct nand_chip. Tested on a custom board, where the CPU is halted without this patch. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09nand: arasan_nfc: Fixed NAND write issueVipul Kumar
In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed to 0xFFFF and the same macro is used in nand write and so that getting nand write error. This patch reverted this macro to the 0xFFFF0000 and used ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function which is equal to 0xFFFF. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-04Merge git://git.denx.de/u-boot-sunxiTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-03sunxi: move the NAND parameters to KconfigMiquel Raynal
Move the NAND parameters from defconfig files to Kconfig for SUNXI architecture only. Fort now only the CHIP pro is migrated. It would have been better to convert this defconfig entry to Kconfig for all supported machines/architectures but it has been abandoned due to a fairly high amount of errors reported by the moveconfig.py tool. This is due to defines quite often being multiplications of values/other defines not correctly handled. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03sunxi: make NAND_SUNXI use ARCH_SUNXI as default in KconfigMiquel Raynal
Remove NAND_SUNXI from the CHIP pro defconfig to be automatically selected depending on the state of ARCH_SUNXI. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03sunxi: automatically select SPL_NAND_SUPPORT in KconfigMiquel Raynal
Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the number of entries to add in defconfig files when adding NAND support. For now, the only board using it is the CHIP pro. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03sunxi: allow NAND support to be compiled for sun8i platformsMiquel Raynal
Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I in Kconfig. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: use PIO instead of DMAMiquel Raynal
SPL support was first written to support only the earlier generations of Allwinner SoCs, and was only really enabled on the A13 / GR8. However, those old SoCs had a DMA engine that has been replaced since the A31 by another DMA controller that is no longer compatible. Since the code directly uses that DMA controller, it cannot operate properly on the later SoCs, while the NAND controller has not changed. There's two paths forward, the first one would have been to add support for that DMA controller too, the second to just remove the DMA usage entirely and rely on PIO. The later has been chosen because CPU overload at this stage is not an issue and it makes the driver more generic, and easier to understand. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: declare the ecc_bytes array globallyMiquel Raynal
Move the ecc_bytes array out of nand_max_ecc_strength() for future use by nand_read_page(). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: make the reset column helper more genericMiquel Raynal
Prepare the future use of an helper to move the data pointer (the column) of the NAND chip by renaming nand_reset_column() to nand_change_column(). Resetting the column is just a matter of giving 0 as argument. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: ensure enough time has passed after changing the columnMiquel Raynal
When changing the column, the ONFI specification states that a minimum time of tCCS (Change Column Setup time) must elapse between the last address cycle is asserted on the bus and the first data cycle is clocked. An usual value for average NANDs is 500 nanoseconds. Round it up to 1 microsecond to be safe. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: create an helper to handle command executionMiquel Raynal
Executing a command is matter of always doing the following sequence: * Waiting for the FIFO to be empty so we can fill it with the new command. * Clearing the status register. * Writing the command in the FIFO. * Waiting for the command to finish. Add a nand_exec_cmd() helper to handle this instead of repeating the logic through the various functions. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: add missing status clearMiquel Raynal
It is best practice to always clear the status register before executing a command to be sure that the status read afterwards is relevant. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helperMiquel Raynal
One bit in the control registers indicates if the NAND controller is ready to receive a new command. Otherwise, the command FIFO is full and we should wait for this bit to flip. It then states that the last command has been processed and the FIFO is now free to welcome another command. Add this sanity check before starting any new command. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: introduce the nand_wait_int() helperMiquel Raynal
The pattern of polling on a status register until a bit is set or a timeout occurs is repeated multiple times in the driver. Mutualize the code by introducing the nand_wait_int() helper that does wait for the bit to flip or returns an error in case of timeout. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: fix typo on register nameMiquel Raynal
Change NFC_SEND_ADR to NFC_SEND_ADDR. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: fix second case of modulo by zero errorMiquel Raynal
In the nand_read_buffer() step, the seed is calculated by doing a modulo by conf->nseeds which is always zero when not using the randomizer (most of SLC NANDs). This situation turns out to lead to a run time freeze with certain toolchains. Derive this seed only when the randomizer is enabled (and conf->nseeds logically not zero), exactly like what has been done before with an identical situation, see commit ea3f750c73e3 ("nand: sunxi: Fix modulo by zero error"). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03mtd: nand: sunxi: fix ECC strength choiceMiquel Raynal
When the requested ECC strength does not exactly match the strengths supported by the ECC engine, the driver is selecting the closest strength meeting the 'selected_strength > requested_strength' constraint. Fix the fact that, in this particular case, ecc->strength value was not updated to match the 'selected_strength'. For instance, one can encounter this issue when no ECC requirement is filled in the device tree while the NAND chip minimum requirement is not a strength/step_size combo natively supported by the ECC engine. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-23arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or moreVipul Kumar
NAND erase was not happening for size 1GiB or more. Erase command was executing successfully but in actual, it was not erasing. This patch fixed erase issue for 1 GiB or more size nand. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-19nand: Remove unused ppc4xx NAND driver and referencesStefan Roese
ppc4xx support was removed some time ago. Lets remove the now unused NAND driver and all its references for this platform as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: Scott Wood <oss@buserror.net>
2018-02-08Convert CONFIG_APBH_DMA et al to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_APBH_DMA CONFIG_APBH_DMA_BURST CONFIG_APBH_DMA_BURST8 Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Stefan Agner <stefan.agner@toradex.com> [trini: Add in MMC as well] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-08Convert CONFIG_NAND_MXS to KconfigStefan Agner
This converts CONFIG_NAND_MXS to Kconfig. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-01-30nand: arasan: Select CONFIG_SYS_NAND_SELF_INITEzequiel Garcia
The Arasan NFC driver requires the self-init mode, so it should select it. Instead of having the config header define the macro, it's cleaner to select the option at the Kconfig level. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30nand: arasan_nfc: Use the calculated ecc address for updating ecc registerSiva Durga Prasad Paladugu
This patch corrects the ecc address calculation before updating to ecc register. The ecc address has to be calculated based on page, oob and ecc sizes of the device. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30nand: arasan_nfc: Add support for ondie eccSiva Durga Prasad Paladugu
This patch adds support for ondie ecc. As of now this adds support for micron parts which supports ondie ecc. Didn't found any better way to detect ondie ecc support by a device except sorting out with manufacture and device id's. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30nand: arasan_nfc: Move common ecc struct initialization init routineSiva Durga Prasad Paladugu
Move common part of ecc structure initialization to arasan_nand_init() routine. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-08mtd: nand: mxs_nand_spl: Remove nand size printJagan Teki
It is not much needed to print nand size in SPL during nand boot, and most of nand spl drivers doesn't print the same. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-12-12mtd: nand: denali: make NAND_DENALI unconfigurable optionMasahiro Yamada
denali.c has no driver entry in itself. It makes sense only when compiled together with denali_dt.c Let NAND_DENALI_DT select NAND_DENALI, and hide NAND_DENALI from the Kconfig menu. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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