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2018-01-08mtd: nand: mxs_nand_spl: Remove nand size printJagan Teki
It is not much needed to print nand size in SPL during nand boot, and most of nand spl drivers doesn't print the same. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-12-19Merge git://git.denx.de/u-boot-spiTom Rini
2017-12-19mtd/spi: fix block count for is25lq040bSean Nyekjaer
This spi-nor is 4Mbit/512KB Fixes: b4fbcbc5a5 ("mtd/spi: add support for is25lq040b") Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-12-12mtd: nand: denali: make NAND_DENALI unconfigurable optionMasahiro Yamada
denali.c has no driver entry in itself. It makes sense only when compiled together with denali_dt.c Let NAND_DENALI_DT select NAND_DENALI, and hide NAND_DENALI from the Kconfig menu. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04Merge git://git.denx.de/u-boot-uniphierTom Rini
2017-12-04Merge git://git.denx.de/u-boot-cfi-flashTom Rini
2017-12-04mtd: nand: denali: consolidate include directivesMasahiro Yamada
Include necessary headers explicitly without relying on indirect header inclusion. <common.h>, <malloc.h> are unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: nand: denali_dt: replace printf() with pr_err()Masahiro Yamada
The Linux derived log functions can be used anywhere and easily turned on/off by CONFIG_LOGLEVEL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: nand: Rename nand.h into rawnand.hMasahiro Yamada
This header was renamed to rawnand.h in Linux. The following is the corresponding commit in Linux. commit d4092d76a4a4e57b65910899948a83cc8646c5a5 Author: Boris Brezillon <boris.brezillon@free-electrons.com> Date: Fri Aug 4 17:29:10 2017 +0200 mtd: nand: Rename nand.h into rawnand.h We are planning to share more code between different NAND based devices (SPI NAND, OneNAND and raw NANDs), but before doing that we need to move the existing include/linux/mtd/nand.h file into include/linux/mtd/rawnand.h so we can later create a nand.h header containing all common structure and function prototypes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: nand: denali: remove ad-hoc board_nand_init() entryMasahiro Yamada
This driver is highly dependent on the configuration from denali_dt.c Please enable CONFIG_NAND_DENALI_DT if you use this driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: nand: denali: remove bogus __maybe_unusedMasahiro Yamada
denali_setup_data_interface() is always used. I put __maybe_unused for a temporal use, then forgot to delete it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: cfi: Fix checking status register featureYork Sun
Commit 72443c7f7d21 ("mtd: cfi: Add support for status register polling") added a feature check to determine if status register is available for certain flash chips. The "lower software bits" register used to determine this feature is not backward compati- ble. Older flash chips without this feature has reserved value 0xff. Instead of checking "lower software bits" register, use CFI primary vendor-specific extended query. Since CFI version 1.4, software features can be read from offset 0x53 according to document AN201168 from Cypress. Signed-off-by: York Sun <york.sun@nxp.com> CC: Marek Vasut <marek.vasut@gmail.com> Tested-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30fix: nand: pxa3xx: fix defined but not used warningsSean Nyekjaer
bbt_mirror_descr and bbt_main_descr is defined but not used when compiling without CONFIG_SYS_NAND_USE_FLASH_BBT set. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-29Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini u-boot configurations (cse) - dts updates - config/defconfig updates in connection to Kconfig changes - Fix psu_init handling ZynqMP: - SPL fixes - Remove slcr.c - Fixing r5 startup sequence - Add support for external pmufw - Add support for new ZynqMP chips - dts updates - Add support for zcu102 rev1.0 board Drivers: - nand: Support external timing setting and board init - ahci: Fix wording - axi_emac: Wait for bit, non processor mode, readl/write conversion - zynq_gem: Fix SGMII/PCS support
2017-11-29mtd: nand: zynq: Add support for the NAND lock/unlock operationJoe Hershberger
Zynq NAND driver is not support for NAND lock or unlock operation. Hence, accidentally write into the critical NAND region might cause data corruption to occur. This commit is to add NAND lock/unlock command into NAND SMC register set for NAND lock/unlock operaion. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Scott Wood <oss@buserror.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29mtd: zynq: nand: Move board_nand_init() function to board.cWilson Lee
Putting board_nand_init() function inside NAND driver was not appropriate due to it doesn't allow board vendor to customise their NAND initialization code such as adding NAND lock/unlock code. This commit was to move the board_nand_init() function from NAND driver to board.c file. This allow customization of board_nand_init() function. Signed-off-by: Wilson Lee <wilson.lee@ni.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Cc: Scott Wood <oss@buserror.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29mtd: nand: denali: sync with Linux 4.15-rc1Masahiro Yamada
I largely reworked the Denali NAND controller driver in Linux. This commit imports the improvements from Linux. The code is almost synced with Linux 4.15-rc1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: introduce NAND_ROW_ADDR_3 flagMasahiro Yamada
Several drivers check ->chipsize to see if the third row address cycle is needed. Instead of embedding magic sizes such as 32MB, 128MB in drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up. Since nand_scan_ident() knows well about the device, it can handle this properly. The flag is set if the row address bit width is greater than 16. Delete comments such as "One more address cycle for ..." because intention is now clear enough from the code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Wenyou Yang <wenyou.yang@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 14157f861437ebe2d624b0a845b91bbdf8ca9a2d]
2017-11-29mtd: nand: add generic helpers to check, match, maximize ECC settingsMasahiro Yamada
Driver are responsible for setting up ECC parameters correctly. Those include: - Check if ECC parameters specified (usually by DT) are valid - Meet the chip's ECC requirement - Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set The logic can be generalized by factoring out common code. This commit adds 3 helpers to the NAND framework: nand_check_ecc_caps - Check if preset step_size and strength are valid nand_match_ecc_req - Match the chip's requirement nand_maximize_ecc - Maximize the ECC strength To use the helpers above, a driver needs to provide: - Data array of supported ECC step size and strength - A hook that calculates ECC bytes from the combination of step_size and strength. By using those helpers, code duplication among drivers will be reduced. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 2c8f8afa7f92acb07641bf95b940d384ed1d0294]
2017-11-29mtd: nand: Pass the CS line to ->setup_data_interface()Boris Brezillon
Some NAND controllers can assign different NAND timings to different CS lines. Pass the CS line information to ->setup_data_interface() so that the NAND controller driver knows which CS line is concerned by the setup_data_interface() request. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 104e442a67cfba4d0cc982384761befb917fb6a1] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: allow drivers to request minimum alignment for passed bufferMasahiro Yamada
In some cases, nand_do_{read,write}_ops is passed with unaligned ops->datbuf. Drivers using DMA will be unhappy about unaligned buffer. The new struct member, buf_align, represents the minimum alignment the driver require for the buffer. If the buffer passed from the upper MTD layer does not have enough alignment, nand_do_*_ops will use bufpoi. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 477544c62a84d3bacd9f90ba75ffc16c04d78071]
2017-11-29mtd: nand: Wait for PAGEPROG to finish in drivers setting ↵Boris Brezillon
NAND_ECC_CUSTOM_PAGE_ACCESS Drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS are supposed to handle the full read/write page sequence, and waiting for a page to actually be programmed is part of this write-page sequence. This is also what is done in ->write_oob_xxx() hooks, so let's do that in ->write_page_xxx() as well to make it consistent. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 41145649f4acb30249b636b945053db50c9331c5] [masahiro: There is no driver setting NAND_ECC_CUSTOM_PAGE_ACCESS in U-Boot. No driver is affected by this change.] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Drop the ->errstat() hookBoris Brezillon
The ->errstat() hook is no longer implemented NAND controller drivers. Get rid of it before someone starts abusing it. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 7d135bcced20be2b50128432c5426a7278ec4f6d] [masahiro: modify davinci_nand.c for U-Boot] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Drop unused cached programming supportBoris Brezillon
Cached programming is always skipped, so drop the associated code until we decide to really support it. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 0b4773fd1649e0d418275557723a7ef54f769dc9] [masahiro: modify davinci_nand.c for U-Boot] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: add mtd_ooblayout_xxx() helper functionsBoris Brezillon
In order to make the ecclayout definition completely dynamic we need to rework the way the OOB layout are defined and iterated. Create a few mtd_ooblayout_xxx() helpers to ease OOB bytes manipulation and hide ecclayout internals to their users. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 75eb2cec251fda33c9bb716ecc372819abb9278a] [masahiro: cherry-pick more code from adbbc3bc827eb1f43a932d783f09ba55c8ec8379] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Support controllers with custom pageMarc Gonzalez
If your controller already sends the required NAND commands when reading or writing a page, then the framework is not supposed to send READ0 and SEQIN/PAGEPROG respectively. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 3371d663bb4579f1b2003a92162edd6d90edd089] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Add a few more timings to nand_sdr_timingsBoris Brezillon
Add the tR_max, tBERS_max, tPROG_max and tCCS_min timings to the nand_sdr_timings struct. Assign default/safe values for the statically defined timings, and extract them from the ONFI parameter table if the NAND is ONFI compliant. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> [Linux commit: 204e7ecd47e26cc12d9e8e8a7e7a2eeb9573f0ba Fixup commit: 6d29231000bbe0fb9e4893a9c68151ffdd3b5469] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Fix data interface configuration logicBoris Brezillon
When changing from one data interface setting to another, one has to ensure a specific sequence which is described in the ONFI spec. One of these constraints is that the CE line has go high after a reset before a command can be sent with the new data interface setting, which is not guaranteed by the current implementation. Rework the nand_reset() function and all the call sites to make sure the CE line is asserted and released when required. Also make sure to actually apply the new data interface setting on the first die. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: d8e725dd8311 ("mtd: nand: automate NAND timings selection") Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> [Linux commit: 73f907fd5fa56b0066d199bdd7126bbd04f6cd7b] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: automate NAND timings selectionBoris Brezillon
The NAND framework provides several helpers to query timing modes supported by a NAND chip, but this implies that all NAND controller drivers have to implement the same timings selection dance. Also currently NAND devices can be resetted at arbitrary places which also resets the timing for ONFI chips to timing mode 0. Provide a common logic to select the best timings based on ONFI or ->onfi_timing_mode_default information. Hook this into nand_reset() to make sure the new timing is applied each time during a reset. NAND controller willing to support timings adjustment should just implement the ->setup_data_interface() method. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [Linux commit: d8e725dd831186a3595036b2b1df9f68cbc6efa3] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Expose data interface for ONFI mode 0Sascha Hauer
The nand layer will need ONFI mode 0 to use it as timing mode before and right after reset. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 6e1f9708dbf3c50a8da93c1952a01a7a2acb5e66] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: convert ONFI mode into data interfaceSascha Hauer
struct nand_data_interface is the designated type to pass to the NAND drivers to configure the timing. To simplify further patches convert the onfi_sdr_timings array from type struct nand_sdr_timings nand_data_interface. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: b1dd3ca203fccd111926c3f6ac59bf903ec62b05] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Create a NAND reset functionSascha Hauer
When NAND devices are resetted some initialization may have to be done, like for example they have to be configured for the timing mode that shall be used. To get a common place where this initialization can be implemented create a nand_reset() function. This currently only issues a NAND_CMD_RESET to the NAND device. The places issuing this command manually are replaced with a call to nand_reset(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 2f94abfe35b210e7711af9202a3dcfc9e779219a] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Add an option to maximize the ECC strengthBoris Brezillon
The generic NAND DT bindings allows one to tweak the ECC strength and step size to their need. It can be used to lower the ECC strength to match a bootloader/firmware config, but might also be used to get a better reliability. In the latter case, the user might want to use the maximum ECC strength without having to explicitly calculate the exact value (this value not only depends on the OOB size, but also on the NAND controller, and can be tricky to extract). Add a generic 'nand-ecc-maximize' DT property and the associated NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best ECC strength and step-size on their own. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> [Linux commit: ba78ee00e1ff84de9b3ad33edbd3ec599099ee82] [masahiro: of_property_read_bool -> fdt_getprop for U-Boot] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29bitops: collect BIT macros to include/linux/bitops.hMasahiro Yamada
Same macros are defined in various places. Collect them into include/linux/bitops.h like Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-28mtd: nand: zynq: Add a config option to use 1st stage bootloader timingJeff Westfahl
In legacy method, 1st stage bootloader was used to configure the HW setting such as NAND timing. Hence, adding a config option in Zynq NAND driver for the compatibility of device that using 1st stage bootloder instead of U-boot SPL. This commit is to add config option CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS that allow NAND driver use timing values set by the 1st stage bootloader, instead of the hard-coded values in the Zynq NAND driver. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> Signed-off-by: Wilson Lee <wilson.lee@ni.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Scott Wood <oss@buserror.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-21mtd/spi: add support for is25lq040bSean Nyekjaer
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-20ubi: no NULL check needed before kmem_cache_destroyHeinrich Schuchardt
kmem_cache_destroy calls free which checks for NULL. Problem was indicated by coccinelle. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-11-17omap2: nand: Make NAND_OMAP_GPMC_PREFETCH defaultTom Rini
This option provides better performance and should really always be enabled. Make this be default y. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2017-11-14mtd: nand: fsl-ifc: fix support of multiple NAND devicesKurt Kanzenbach
Currently the chipselect used to identify the corresponding NAND chip is stored at the controller and only set during fsl_ifc_chip_init(). This way, only the last NAND chip is working, as the previous value of cs_nand gets overwritten. In order to solve this issue the chipselect is computed on demand by evaluating the bank variable. Thus, the correct chipselect for each NAND chip operation is used. Tested on hardware with two NAND chips connected to the IFC controller. Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de> Acked-by: Scott Wood <oss@buserror.net> [YS: reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-25SPL: SPI: select SPL_SPI_FLASH_SUPPORT on SPL_SPI_SUNXIAndre Przywara
The Allwinner SPI flash SPL boot support is guarded by the SPL_SPI_SUNXI symbol. But despite its generic name, the actual only use case for this is to provide SPI flash support to the SPL, which requires CONFIG_SPL_SPI_FLASH_SUPPORT to be defined. Select this symbol from the SPL_SPI_SUNXI Kconfig definition. This avoids doing this explicitly in the defconfig, and fixes SPI booting on the Pine64 SoPine (and -LTS version) and the OrangePi Win board (both with SPI flash). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-23mtd: replace MTDDEBUG() with pr_debug()Masahiro Yamada
In old days, the MTD subsystem in Linux had debug facility like DEBUG(MTD_DEBUG_LEVEL1, ...). They were all replaced with pr_debug() until Linux 3.2. See Linux commit 289c05222172 ("mtd: replace DEBUG() with pr_debug()"). U-Boot still uses similar macros. Covert all of them for easier sync. Done with the help of Coccinelle. The semantic patch I used is as follows: // <smpl> @@ expression e1, e2; @@ -MTDDEBUG(e1, e2) +pr_debug(e2) @@ expression e1, e2; @@ -MTDDEBUG(e1, e2, +pr_debug(e2, ...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-20Convert CONFIG_NAND_OMAP_GPMC et al and CONFIG_NAND_MXC to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_NAND_MXC CONFIG_NAND_OMAP_GPMC CONFIG_NAND_OMAP_GPMC_PREFETCH CONFIG_NAND_OMAP_ELM CONFIG_SPL_NAND_AM33XX_BCH CONFIG_SPL_NAND_SIMPLE CONFIG_SYS_NAND_BUSWIDTH_16BIT Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> [trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues, add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-18Merge git://git.denx.de/u-boot-spiTom Rini
2017-10-16Drop CONFIG_HAS_DATAFLASHTuomas Tynkkynen
Last user of this option went away in commit: fdc7718999 ("board: usb_a9263: Update to support DT and DM") Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-10-15mtd: nand: denali_dt: add clock supportMasahiro Yamada
Enable clock in the probe hook. The clock rate will be necessary when setup_data_interface hook is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15mtd: nand: do not check R/B# for CMD_SET_FEATURES in nand_command(_lp)Masahiro Yamada
Set Features (0xEF) command toggles the R/B# pin after 4 sub feature parameters are written. Currently, nand_command(_lp) calls chip->dev_ready immediately after the address cycle because NAND_CMD_SET_FEATURES falls into default: label. No wait is needed at this point. If you see nand_onfi_set_features(), R/B# is already cared by the chip->waitfunc call. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [ Linux commit: c5d664aa5a4c4b257a54eb35045031630d105f49 ]
2017-10-15mtd: nand: do not check R/B# for CMD_READID in nand_command(_lp)Masahiro Yamada
Read ID (0x90) command does not toggle the R/B# pin. Without this patch, NAND_CMD_READID falls into the default: label, then R/B# is checked by chip->dev_ready(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [ Linux commit: 3158fa0e739615769cc047d2428f30f4c3b6640e ]
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-27sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operationLukasz Majewski
The content of Bank Address Register (BAR) is volatile. It is cleared after power cycle or reset command (RESET F0h). Some memories (like e.g. s25fl256s) use it to access memory larger than 0x1000000 (16 MiB). The problem shows up when one: 1. Reads/writes/erases memory > 16 MiB 2. Calls "reset" u-boot command (which is not causing BAR to be cleared) In the above scenario, the SoC ROM sends 0x000000 address to read SPL. Unfortunately, the BA24 bit is still set and hence it receives content from 0x1000000 (16 MiB) memory address. As a result the SoC aborts and we hang. Only power cycle can take the SoC out of this state. How to reproduce/test: sf probe; sf erase 0x1200000 0x800000; reset sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset sf probe; sf read 0x11000000 0x1200000 0x800000; reset Signed-off-by: Lukasz Majewski <lukma@denx.de> [Fixed comment text on clean_bar function] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-27SPL: SPI: sunxi: add SPL FIT image supportAndre Przywara
The sunxi-specific SPI load routine only knows how to load a legacy U-Boot image. Teach it how to handle FIT images as well, simply by providing the existing SPL FIT loader with the right loader routine to access the SPI NOR flash. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Peter Kosa <kope@madnet.sk> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
generated by cgit (git 2.34.1) at 2024-12-26 22:22:20 +0000