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path: root/drivers/net/tsec.c
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2009-02-22Added Vitesse VSC8211 definitions to TSEC driverPieter Henning
Added the struct containing PHY settings for the Vitesse VSC8211 phy to the phy_info list in tsec.c Signed-off-by: Pieter Henning <phenning@vastech.co.za> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-02-09tsec: Fix a bug in soft-resettingAndy Fleming
SOFT_RESET must be asserted for at least 3 TX clocks. Usually, that's about 30 clock cycles, so it's been mostly working. But we had no guarantee, and at slower bitrates, it's just over a microsecond (over 1000 clock cycles). This enforces a 2 microsecond gap between assertion and deassertion. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-01-28Marvell 88E1118 interrupt fixRon Madrid
This patch adjusts the LED control so that interrupt lines are not reading LEDs and effectively causing indefinite interrupts to the controller. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-12-04net: tsec: Fix Marvell 88E1121R phy initAnatolij Gustschin
This patch tries to ensure that phy interrupt pin won't be asserted after booting. We experienced following issues with current 88E1121R phy init: Marvell 88E1121R phy can be hardware-configured to share MDC/MDIO and interrupt pins for both ports P0 and P1 (e.g. as configured on socrates board). Port 0 interrupt pin will be shared by both ports in such configuration. After booting Linux and configuring eth0 interface, port 0 phy interrupts are enabled. After rebooting without proper eth0 interface shutdown port 0 phy interrupts remain enabled so any change on port 0 (link status, etc.) cause assertion of the interrupt. Now booting Linux and configuring eth1 interface will cause permanent phy interrupt storm as the registered phy 1 interrupt handler doesn't acknowledge phy 0 interrupts. This of course should be fixed in Linux driver too. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-13enable 10/100M at VSC8601 at tsec driverAndre Schwarz
Currently VSC8601 doesn't link with 10/100M partners if the EEPROM/Strapping is not set up. Setting the auto-neg register fixes this. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-16Support for multiple SGMII/TBI interfaces for TSEC ethernetPeter Tyser
Fix TBI PHY accesses to use the proper offset in CPU register space. The previous code would incorrectly access the TBI PHY by reading/writing to CPU register space at the same location as would be used to access external PHYs. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
2008-09-02Add SGMII support to the tsecAndy Fleming
Adds support for configuring the TBI to talk properly with the SerDes. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02Pass in tsec_info struct through tsec_initializeAndy Fleming
The tsec driver contains a hard-coded array of configuration information for the tsec ethernet controllers. We create a default function that works for most tsecs, and allow that to be overridden by board code. It creates an array of tsec_info structures, which are then parsed by the corresponding driver instance to determine configuration. Also, add regs, miiregs, and devname fields to the tsec_info structure, so that we don't need the kludgy "index" parameter. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02tsec: Move tsec.h to include/Andy Fleming
This is to prepare the way for board code passing in the tsec_info structure Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02PHY: Add support for the M88E1121R Marvell chip.Sergei Poselenov
Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-06-09net: Conditional COBJS inclusion of network driversShinya Kuribayashi
Replace COBJS-y with appropriate driver config names. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-05-23Add Marvell 88E1118 support for TSECRon Madrid
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-05-04drivers/net/tsec.c: Fix typo.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-03TSEC: add config options for VSC8601 RGMII PHYAndre Schwarz
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx and Tx clock lines. They are configured using 2 bits in extended register 0x17. Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Ben Warren <biggerbadderben@gmail.com> -- drivers/net/tsec.c | 6 ++++++ drivers/net/tsec.h | 3 +++ 2 files changed, 9 insertions(+), 0 deletions(-)
2008-03-31Add Vitesse 8601 support to TSEC driverTor Krill
Add phy_info for Vitesse VSC8601. Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation. Signed-off-by: Tor Krill <tor@excito.com> Reviewed-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-03-25tsec: fix link detection for the RTL8211B PHYAnton Vorontsov
RTL8211B sets link state register after autonegotiation complete, so with bootdelay=0 RTL8211B will report lack of the link. To fix this, we should wait for aneg to complete, even if the link is currently down. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-16TSEC: Add the support for RealTek RTL8211B PHYDave Liu
Add the support of RealTek RTL8211B PHY, the RTL8211B PHY only supports RGMII and MII mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-01-16TSEC driver: Change MDIO support to allow access to any PHYs on the MDIO busmichael.firth@bt.com
The current TSEC driver limits MDIO access to the devices that have been configured as attached to a TSEC MAC. This patch allows access to any PHY device on the MDIO bus through the 'mii' commands. Signed-off-by: Michael Firth <michael.firth@bt.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-01-10Fix Ethernet init() return codesBen Warren
Change return values of init() functions in all Ethernet drivers to conform to the following: >=0: Success <0: Failure All drivers going forward should return 0 on success. Current drivers that return 1 on success were left as-is to minimize changes. Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Acked-By: Timur Tabi <timur@freescale.com>
2008-01-08mpc83xx: Add the support of MPC837xEMDS boardDave Liu
The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-11-25drivers/net : move net drivers to drivers/netJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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