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Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early
verion silicons. This workaround detects if the eTSEC Rx logic is properly
initialized, and reinitialize the eTSEC Rx logic.
Signed-off-by: Gong Chen <g.chen@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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This converts tsec to use the new PHY Lib. All of the old PHY support
is ripped out. The old MDIO driver is split off, and placed in
fsl_mdio.c. The initialization is modified to initialize the MDIO
driver as well. The powerpc config file is modified to configure PHYLIB
if TSEC_ENET is configured.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
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This is merely a rearrangement. No changes to the code, except
to remove now-useless declarations.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Li Yang <leoli@freescale.com>
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The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The following commit:
commit 46e91674fb4b6d06c6a4984c0b5ac7d9a16923f4
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Tue Nov 3 17:52:07 2009 -0600
tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode
Removed setting Auto-Neg by default, however this is believed to be
proper default configuration for initialization of the TBI interface.
Instead we explicitly set CONFIG_TSEC_TBICR_SETTINGS for the
XPedite5370 & XPedite5500 boards that use a Broadcomm PHY which require
Auto-Neg to be disabled to function properly.
This addresses a breakage on the P2020 DS & MPC8572 DS boards when used
with an SGMII riser card. We also remove setting
CONFIG_TSEC_TBICR_SETTINGS on the P1_P2_RDB family of boards as now the
default setting is sufficient for them.
Additionally, we clean up the code a bit to remove an unnecessary second
define.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Peter Tyser <ptyser@xes-inc.com>
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The driver name does not need to be writable, so constify it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The Ethernet initialization functions are supposed to return the number of
devices initialized, so fix tsec_eth_init() so that they returns the number of
TSECs initialized, instead of just zero. This is safe because the return value
is currently ignored by all callers, but now they don't have to ignore it.
In general, if an function initializes only one device, then it should return
a negative number if there's an error. If it initializes more than one device,
then it should never return a negative number.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII.
Current TBI PHY settings for SGMII mode cause link problems on
this platform, link never comes up.
Fix this by making TBI PHY settings configurable and add a working
configuration for P2020RDB.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Acked-by: Andy Fleming <afleming@freescale.com>
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When gracefully stopping the controller, the driver was continuing if
*either* RX or TX had stopped. We need to wait for both, or the
controller could get into an invalid state.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The TSEC_FIBER flag should be set when a PHY is operating with an
external fiber interface. Currently it is only used to notify a user
that the PHY is operating in fiber mode.
A short description was also added to the other TSEC flag defines so
that it is clear how they differ from one another.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The BCM5482 PHY supports both copper and fiber as an ethernet medium.
By enabling its copper/fiber mode auto-detection feature it can
dynamically determine if it should be configured for copper or fiber.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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- Cleanup formatting of phy_info structures
- Fix lines > 80 chars
- Fix some random indentation inconsistencies
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This is generally good practice and saves ~150 bytes.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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- Remove unnecessary printing "Enet starting in <speed>/<duplex>"
This same information is already printed during normal ethernet
operation in the form "Speed: 1000, full duplex".
- Add a check for link before determining link speed and duplex
If there is no link, speed/duplex don't matter. This also removes
the annoying and unneeded "Auto-neg error, defaulting to 10BT/HD"
message that occurs when no link is detected.
- Whitespace and line > 80 characters cleanup
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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In SGMII mode the link between a processor's internal TBI PHY and an
external PHY should always be 1000Mbps, full duplex. Also, the SGMII
interface between an internal TBI PHY and external PHY does not
support in-band auto-negotation.
Previously, when configured for SGMII mode a TBI PHY would attempt to
restart auto-negotation during initializtion. This auto-negotation
between a TBI PHY and external PHY would fail and result in unusable
ethernet operation.
Forcing the TBI PHY and and external PHY to link at 1000Mbps full duplex
in SGMII mode resolves this issue of auto-negotation failing.
Note that 10Mbps and 100Mbps operation is still possible on the external
side of the external PHY even when SGMII is operating at 1000Mbps.
The SGMII interface still operates at 1000Mbps, but each byte of data
is repeated 100 or 10 times for 10/100Mbps and the external PHY handles
converting this data stream into proper 10/100Mbps signalling.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Moved the mdio regs out of the tsec structure,and
provided different offsets for tsec base and mdio
base so that provision for etsec2.0 can be provided.
This patch helps in providing the support for etsec2.0
In etsec2.0, the MDIO register space and the etsec reg
space are different.
Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into
platform specific files.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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complete
if you don't have firmware installed for the PHY to come to life, this
wait can be painful - let's give the option to avoid it if we want.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Previously, waiting for auto-negotiation would only occur if a valid
link had been detected. Problems arose when attempting to use a
tsec immediately after bootup but before link was achieved, eg:
=> dhcp
Auto-neg error, defaulting to 10BT/HD
eTSEC1: No link.
Auto-neg error, defaulting to 10BT/HD
eTSEC2: No link.
=>
With this patch applied the same operation as above resulted in:
=> dhcp
Waiting for PHY auto negotiation to complete. done
Enet starting in 1000BT/FD
Speed: 1000, full duplex
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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"All Rights Reserved" conflicts with the GPL.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
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These PHYs are on P2020RDB platform.
Also revamped Freescale copyright message in drivers/net/tsec.c.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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rules warning
fix this gcc 4.4 warning:
tsec.c: In function 'tsec_init':
tsec.c:200: warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Zach LeRoy <zleroy@xes-inc.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Commit af1c2b84 added a generic phy support, with an ID of zero
and a 32 bit mask; meaning that it will match on any PHY ID.
The problem is that there is a test that checked if a matching
PHY was found, and if not, it printed the non-matching ID.
But since there will always be a match (on the generic PHY,
worst case), this test will never trip.
In the case of a misconfigured PHY address, or of a PHY that
isn't explicitly supported outside of the generic support,
you will never see the ID of 0xffffffff, or the ID of the
real (but unsupported) chip. It will silently fall through
onto the generic support.
This change makes that test useful again, and ensures that
the selection of generic PHY support doesn't happen without
some sort of notice. It also makes it explicitly clear that
the generic PHY must be last in the PHY table.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Andy Fleming <afleming@freescale.com>
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Added the struct containing PHY settings for the Vitesse VSC8211 phy to
the phy_info list in tsec.c
Signed-off-by: Pieter Henning <phenning@vastech.co.za>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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SOFT_RESET must be asserted for at least 3 TX clocks. Usually, that's about 30
clock cycles, so it's been mostly working. But we had no guarantee, and at
slower bitrates, it's just over a microsecond (over 1000 clock cycles). This
enforces a 2 microsecond gap between assertion and deassertion.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This patch adjusts the LED control so that interrupt lines are not reading LEDs
and effectively causing indefinite interrupts to the controller.
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:
Marvell 88E1121R phy can be hardware-configured
to share MDC/MDIO and interrupt pins for both ports
P0 and P1 (e.g. as configured on socrates board).
Port 0 interrupt pin will be shared by both ports
in such configuration. After booting Linux and
configuring eth0 interface, port 0 phy interrupts
are enabled. After rebooting without proper eth0
interface shutdown port 0 phy interrupts remain
enabled so any change on port 0 (link status, etc.)
cause assertion of the interrupt. Now booting Linux
and configuring eth1 interface will cause permanent
phy interrupt storm as the registered phy 1 interrupt
handler doesn't acknowledge phy 0 interrupts. This
of course should be fixed in Linux driver too.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Currently VSC8601 doesn't link with 10/100M partners if the
EEPROM/Strapping is not set up.
Setting the auto-neg register fixes this.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Fix TBI PHY accesses to use the proper offset in CPU register space. The
previous code would incorrectly access the TBI PHY by reading/writing to CPU
register space at the same location as would be used to access external PHYs.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
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Adds support for configuring the TBI to talk properly with the SerDes.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers. We create a default function that works
for most tsecs, and allow that to be overridden by board code. It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration. Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This is to prepare the way for board code passing in the tsec_info structure
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Replace COBJS-y with appropriate driver config names.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
--
drivers/net/tsec.c | 6 ++++++
drivers/net/tsec.h | 3 +++
2 files changed, 9 insertions(+), 0 deletions(-)
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Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
Signed-off-by: Tor Krill <tor@excito.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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RTL8211B sets link state register after autonegotiation complete,
so with bootdelay=0 RTL8211B will report lack of the link.
To fix this, we should wait for aneg to complete, even if the
link is currently down.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Add the support of RealTek RTL8211B PHY, the RTL8211B
PHY only supports RGMII and MII mode.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The current TSEC driver limits MDIO access to the devices that have been configured as attached
to a TSEC MAC. This patch allows access to any PHY device on the MDIO bus through the 'mii' commands.
Signed-off-by: Michael Firth <michael.firth@bt.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Change return values of init() functions in all Ethernet drivers to conform
to the following:
>=0: Success
<0: Failure
All drivers going forward should return 0 on success. Current drivers that
return 1 on success were left as-is to minimize changes.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Acked-By: Timur Tabi <timur@freescale.com>
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The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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