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2019-04-12net: Add MSCC Jaguar2 network driver.Horatiu Vultur
Add network driver for Microsemi Ethernet switch. It is present on Jaguar2 SoCs. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-04-12ag7xxx: add initial support for s17Rosy Song
S17 ethernet support is for QCA8337N, which used on AP152 (QCA9563) board. It is a 7 ports GbE switch. Signed-off-by: Rosy Song <rosysong@rosinson.com> Changes for v2-v3: - add more commit message for s17 Changes for v4-v5: - coding style cleanup
2019-04-12net: mscc: ocelot: Fix reset of the physHoratiu Vultur
The function mscc_miim_reset resets all the phys, but it is called for each phy separetely. One consequence of this is that the boot time is increased by 2 seconds. The fix consists for calling the mscc_miim_reset function only once for all phys. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12drivers: add ethernet support for qca953x in ag7xxx driverRosy Song
Signed-off-by: Rosy Song <rosysong@rosinson.com>
2019-04-11Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various rmobile fixes
2019-04-09net: sh_eth: Initialize PHY in probe() onceMarek Vasut
Reset and initialize the PHY once in the probe() function rather than doing it over and over again is start() function. This requires us to keep the clock enabled while the driver is in use. This significantly reduces the time between transfers as the PHY doesn't have to restart autonegotiation between transfers, which takes forever. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2019-04-09net: macb: Add small delay after link establishmentStefan Roese
I've noticed that the first ethernet packet after PHY link establishment is not tranferred correctly most of the time on my AT91SAM9G25 board. Here I usually see a timeout of a few seconds, which is quite annoying. Adding a small delay (10ms in this case) after the link establishment helps to solve this problem. With this patch applied, this timeout on the first packet is not seen any more. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wenyou Yang <wenyou.yang@atmel.com> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-08net: dm: fec: Support phy-reset-post-delay propertyAndrejs Cainikovs
As per Linux kernel DT binding doc: - phy-reset-post-delay : Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay milliseconds will be observed after the phy-reset-gpios has been toggled. Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-04-07net: phy: implement fallback mechanism for negative phy adressesHannes Schmelzer
Negative phy-addresses can occour if the caller function was not able to determine a valid phy address (from device-tree for example). In this case we catch this here and search for ANY phy device on the given mdio- bus. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Lukasz Majewski <lukma@denx.de>
2019-03-15drivers: net: ls1088ardb: Fix EC1 and EC2 RCW offsetPramod Kumar
Fix EC1 and EC2 read from correct offset 26, instead of 25 Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15mc : Reduce MC memory size to 128MMeenakshi Aggarwal
ls2088, ls1088 : minimum MC Memory size is 128 MB lx2 : minimum MC memory size is 256 MB Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15driver: net: fsl-mc: Fix DPC MAC address fixupIoana Ciocoi Radulescu
If node /board_info/ports does not exist in the DPC file, function mc_fixup_dpc() will skip not only MAC address fixup, but also the cache flush at the end. This may cause the other fixup changes (e.g. ICID related ones) to be ignored by MC. Fixes: 1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL") Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15drivers: net: ldpaa_eth: check if the dpmac is enabledPankaj Bansal
some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-13drivers/net/fec: phy_init: remove redundant logicHannes Schmelzer
The phy_connect_dev(...) function from phy.c does all the handling (inclusive catching fixed-link). So we drop here the single steps and call just phy_connect_dev(...). Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-27net: macb: Fix GEM hardware detectionAtish Patra
Fix MID bit field check to correctly identify all GEM hardwares. The check is updated as per macb driver in Linux location: <linux_sources>/drivers/net/ethernet/cadence/macb_main.c:259 Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-27net: macb: Fix clk API usage for RISC-V systemsAnup Patel
Don't fail in macb_enable_clk() if clk_enable() returns -ENOSYS because we get -ENOSYS for fixed-rate clocks. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-18arm: socfpga: gen5 enable designware_socfpgaSimon Goldschmidt
Enable the socfpga specific designware ethernet driver by default for socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a MACH_SOCFPGA config. This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-18net: designware: socfpga: adapt to Gen5Simon Goldschmidt
This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-15net: mv88e61xx: fix autonegotiation on portsTim Harvey
phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2019-02-15net: dm: fec: Fix regulator enable when using DM_REGULATORAdam Ford
When DM_REGULATOR is enabled, the driver attempts to call regulator_autoset() which expects the regulators to be on at boot and/or always on and fails if they are not true. For a more generic approach, this patch just calls regulator_set_enable() which shouldn't have such restrictions. Fixes: ad8c43cbcafb ("net: dm: fec: Support the phy-supply binding") Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-01net: Add MSCC Luton networkd driver.Horatiu Vultur
Add network driver for Microsemi Ethernet switch, it is present on Luton SoCs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01net: mscc: Remove unused variablesHoratiu Vultur
Remove unused variables in the struct ocelot_private and make miim variable static. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01net: mscc: Move mac_table_add function into different file.Horatiu Vultur
Move the function mac_table_add into a different file, so it can be reused. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01net: mscc: Move ocelot_send and ocelot_recv in a different file.Horatiu Vultur
This functions can be reused by other MSCC SoCs therefore, make them more generic and move them in separate files. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01net: mscc: Move miim commands into separate file.Horatiu Vultur
Move miim functions that can be shared in a different file inside mscc_eswitch. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01net: mscc: Move ocelot_switch to mscc_eswitch folderHoratiu Vultur
Move file ocelot_switch to mscc_eswitch to prepare to add new net drivers for other MSCC SoCs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-28Enable FEC driver to retrieve PHY address from device treeMartyn Welch
Currently if we have more than one phy on the MDIO bus, we do not have a good mechanism for determining which should be used at runtime. Enable the FEC driver to determine the address for the PHY from the device tree. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-24Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
2019-01-24net: phy: aquantia: Print information on configValentin-catalin Neacsu
Print information about Aquantia system interface and firmware loaded on the phy. Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: aquantia: Enable autoneg when on USXGMIIValentin-catalin Neacsu
If System Interface protocol is USXGMII then enable USXGMII autoneg Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: remove CONFIG_MCAST_TFTPChris Packham
No mainline board enables CONFIG_MCAST_TFTP and there have been compilation issues with the code for some time. Additionally, it has a potential buffer underrun issue (reported as a side note in CVE-2018-18439). Remove the multicast TFTP code but keep the driver API for the future addition of IPv6. Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: move ether_crc to tsec driverChris Packham
ether_crc was added to the core net code in commit 53a5c424bf86 ("multicast tftp: RFC2090") so that other drivers could use it. However the only current user of it is tsec.c so move it there. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: realtek: Add functions to read PHY's extended registersCarlo Caione
According to the datasheet to access the extended registers we have to: 1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ) 2. Read/Write the target Register Data 3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE Standard Registers) Hook the missing functions so that we can use the `mdio rx/wx` command to easily access the extended registers. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: macb: fix mapping of registersRamon Fried
Some architectures (MIPS) needs mapping to access IOMEM. Fix that. Fixes: f1dcc19b213d ("net: macb: Convert to driver model") Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvneta: Add GPIO configuration supportAditya Prayoga
This patch add GPIO configuration support in mvneta driver. Driver will handle PHY reset. GPIO pins should be set in device tree. Ported from mvpp2x [https://patchwork.ozlabs.org/patch/799654/] Initial discussion to port the changes into mvneta [https://patchwork.ozlabs.org/patch/1005765/] Signed-off-by: Aditya Prayoga <aditya@kobol.io> Tested-by: Dennis Gilmore <dgilmore@redhat.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvgbe: fallback phy-mode to GMIIChris Packham
Some existing device trees don't specify a phy-mode so fallback to GMII when a phy-mode is not provided. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: micrel: fix KSZ9031 clock skew for values greater 0psAndreas Pretzsch
For KSZ9021, all skew register fields are 4-bit wide. For KSZ9031, the clock skew register fields are 5-bit wide. The common code in ksz90x1_of_config_group calculating the combined register value checks if the requested value is above the maximum and uses this maximum if so. The calculation of this maximum uses the register width, but the check itself does not. It uses a hardcoded value of 0xf, which is too low in case of the 5-bit clock (0x1f). This detail was probably lost during driver unification. Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps), this silently results in 1860 (== +960ps) instead of the requested one. Fix the check by using the bit width instead of hardcoded value(s). Signed-off-by: Andreas Pretzsch <apr@cn-eng.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvpp2: mdio device per portBaruch Siach
Current code forces all ports on a given Ethernet device to use the same mdio device. In practice different ports might be wired to separate mdio devices. Move the mdio device from the container struct mvpp2 to the per port struct mvpp2_port. Cc: Ken Ma <make@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvpp2: fix lookup of mdio registers base addressBaruch Siach
Current mdio base lookup code relies on a 'reg' property at the upper CP node. There is no 'reg' property there in current DT files of Armada CP110. Use ofnode_get_addr() instead since it provides proper DT address translation. Cc: Ken Ma <make@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: designware: clear padding bytesSimon Goldschmidt
Short frames are padded to the minimum allowed size of 60 bytes. However, the designware driver sends old data in these padding bytes. It is common practice to zero out these padding bytes ro prevent leaking memory contents to other hosts. Fix the padding code to zero out the padded bytes at the end. Tested on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: designware: fix tx packet lengthSimon Goldschmidt
The designware driver has a bug in setting the tx length into the dma descriptor: it always or's the length into the descriptor without zeroing out the length mask before. This results in occasional packets being transmitted with a length greater than they should be (trailer). Due to the nature of Ethernet allowing such a trailer, most packets seem to be parsed fine by remote hosts, which is probably why this hasn't been noticed. Fix this by correctly clearing the size mask before setting the new length. Tested on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-24net: phy: Add clause 45 identifier to phy_devicePankaj Bansal
The phy devices can be accessed via clause 22 or via clause 45. This information can be deduced when we read phy id. if the phy id is read without giving any MDIO Manageable Device Address (MMD), then it conforms to clause 22. otherwise it conforms to clause 45. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: Move fixed link code to separate routineSiva Durga Prasad Paladugu
This patch moves fixed-link functionality code to a separate routine inorder to make it more modular and cleaner. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24zynq-gem: Use appropriate cache flush/invalidate for RX and TXStefan Theil
The cache was only flushed before *transmitting* packets, but not when receiving them, leading to an issue where new packets were handed to the receive handler with old contents in cache. This only happens when a lot of packets are received without sending packages every now and then. Also flushing the receive buffers in the transmit function makes no sense and can be removed. Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-23net: add MSCC Ocelot switch supportGregory CLEMENT
This patch adds support for the Microsemi Ethernet switch present on Ocelot SoCs. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-18Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
Add TFA boot flow for more boards Add TFA boot defconfig for ls1088a and ls2088a. Add dts fixup for PCIe endpoint and root complex.
2019-01-17Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mipsTom Rini
- MIPS: mscc: various enhancements for Luton and Ocelot platforms - MIPS: mscc: added support for Jaguar2 platform - MIPS: optimised SPL linker script - MIPS: bcm6368: fix restart flow issues - MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards - MIPS: mt7688: small fixes and enhancements - mmc: compile-out write support if disabled
2019-01-17fsl-layerscape: dpaa: fix fsl-mc status in fdt with bootefiMian Yousaf Kaukab
fsl-mc lazyapply command applies dpl from efi_exit_boot_services(). Status of fsl-mc node in working fdt is updated at this stage. However, an efi application like grub may already have copied the fdt. So the updates to fdt done at efi_exit_boot_services() may not be visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply command is used. Fixes: b7b8410a8f (ls2080: Exit dpaa only right before exiting U-Boot) Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-16net: bcm6368: fix restart flow issuesÁlvaro Fernández Rojas
Correctly enable/disable bcm6368-net controller to avoid flow issues. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-15Merge tag 'dm-pull-15jan19' of git://git.denx.de/u-boot-dmTom Rini
Fix recent changes to serial API for driver model Buildman clang support and a few fixes Small fixes to 'dm tree' and regmap test Improve sandbox build compatibility A few other minor fixes
generated by cgit (git 2.34.1) at 2025-01-07 15:22:14 +0000