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2018-09-29Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
Switch to driver model for eSDHC on Layerscape SoCs including LS1021A, LS1043A, LS1046A, LS1088A, LS2088A. Switch to driver model for SATA on LS1021A and LS1043A. Add support for LS1012AFRWY rev C board. Enable SMMU for LS1043A.
2018-09-27net: fman: Support both new and legacy FMan CompatiblesZhao Qiang
Recently the FMan Port and MAC compatibles were changed. This patch aligns the FMan Port and MAC compatibles to the new FMan device tree binding document. The FMan device tree binding document can be found in the Linux kernel version 3.18.0, commit 297d35fd2a7d3fbd4e5c0f0c1c18213117ba11ba ./Documentation/devicetree/bindings/powerpc/fsl/fman.txt This patch doesn't affect legacy compatibles support. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> [York S: reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27ls1012a: remove debug info from u-boot logPramod Kumar
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27driver: net: fsl-mc: Memset MC reserve ram memory before usagePrabhakar Kushwaha
Memory reserved for Management Complex needs to be cleaned before any usage. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27u-boot: fixup the iommu-map property of fsl-mc nodeNipun Gupta
The iommu-map property in the fsl-mc node is updated by valid stream-ids by u-boot. This patch is to fixup this property for LS208x and LS1088. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27ppa/fm/qe: use block layer in ppa/fm/qe driverYinbo Zhu
At present the MMC subsystem maintains its own list of MMC devices. This cannot work with driver model when CONFIG_BLK is enabled, use blk_dread to replace previous mmc read interface, use mmc_get_blk_desc to get the mmc device property. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> [York S: reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblazeTom Rini
Xilinx changes for v2018.11 - Handle BOARD_LATE_INIT via Kconfig SPL: - Enable GZIP for all partitions types(not only for kernel) ZynqMP: - Rearrange pmufw version handling - Support newer PMUFW with improved fpga load sequence Zynq: - Cleanup config file - Simplify zybo config by enabling option via Kconfig net: - Fix gems max-speed property reading - Enable support for fixed-link phys
2018-09-27net: zynq_gem: Add support for fixed-link phyMichal Simek
Based on dt-specs fixed-link doesn't require phy-handle to be used. Fix driver to only read phy related setting when phy-handle is found. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-09-26net: zynq_gem: Fix reading of max-speed propertySiva Durga Prasad Paladugu
max-speed property is part of phynode and it has to be read using ofnode_read_u32_default(). This fixes the issue of incorrect max-speed read from DT. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-25drivers: net: cpsw: add support to update phy addressSekhar Nori
On some boards using TI CPSW, it may be possible that PHY address was not latched correctly, and the actual address that the phy responds on is different from that set in device-tree. For example, see this problem report on beaglebone black: https://groups.google.com/d/msg/beagleboard/9mctrG26Mc8/1FuI_i5KW10J Add support to check for this condition and use the detected phy address when its safe to do so. Also, add a public API that exposes the phy address of a given slave. This can be used to update device-tree that is passed to Linux kernel. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-08-17Convert CONFIG_MII et al to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_MII CONFIG_DRIVER_TI_EMAC Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-17Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2018-08-13net: designware: socfpga: Add Arria10 extrasMarek Vasut
Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-08-08fsl/mc: Limit the ethernet name to ETH_NAME_LENPankaj Bansal
The ethernet name should be within the ETH_NAME_LEN, as this is the buffer space allocated to ethernet name. Otherwise, this causes buffer overflow. Reported-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-26net: zynq_gem: convert to use livetreeSiva Durga Prasad Paladugu
This patch updates the zynq gem driver to support livetree. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26drivers: net: zynq_gem: fix phy dt node settingGrygorii Strashko
Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is connected and configured which is not correct. Use struct phydev->node instead. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26drivers: net: cpsw: fix phy dt node settingGrygorii Strashko
Now CPSW driver will overwrite UCLASS_ETH node when PHY is connected and configured which is not correct. Use struct phydev->node instead. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26net: phy: xilinx: switch to use phy_get_ofnode()Grygorii Strashko
Use PHY API phy_get_ofnode() helper to get PHY DT node. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26net: phy: dp83867: switch to use phy_get_ofnode()Grygorii Strashko
Use PHY API phy_get_ofnode() helper to get PHY DT node. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26net: phy: add ofnode node to struct phy_deviceGrygorii Strashko
Now the UCLASS_ETH device "node" field is owerwritten by some network drivers in case of Ethernet PHYs which are linked to UCLASS_ETH device using "phy-handle" DT property and when Ethernet PHY driver needs to read some additional information from DT. In such cases following happens (in general): - network drivers priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); <-- phydev is connected to dev which is UCLASS_ETH device if (priv->phy_of_handle > 0) dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle); <-- phydev->dev->node is overwritten by phy-handle DT node - PHY driver in .config() callback int node = dev_of_offset(dev); <-- PHY driver uses overwritten dev->node const void *fdt = gd->fdt_blob; if (fdtdec_get_bool(fdt, node, "property")) ... As result, UCLASS_ETH device can't be used any more for DT accessing. This patch adds additional ofnode node field to struct phy_device which can be set explicitly by network drivers and used by PHY drivers, so overwriting can be avoided. Also add helper function phy_get_ofnode() which will check and return phy_device->node or dev_ofnode(phydev->dev) for backward compatibility with existing drivers. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26net: phy: Clean up includes of common.hJoe Hershberger
We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26net: phy: dp83867: switch to use ofnode apiGrygorii Strashko
Switch to use more generic ofnode API instead of FDT API. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26net: phy: dp83867: add workaround for incorrect RX_CTRL pin strapMurali Karicheri
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)). It further advises that if a board has this pin strapped in mode 1 and mode 2, then bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. This is to ensure proper operation of PHY. Since it is not possible to detect in software if RX_DV/RX_CTRL pin is incorrectly strapped, add a device-tree property to advertise this and allow corrective action in software. [1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26net: mvgbe: convert to DMChris Packham
Add driver model support to the mvgbe driver. As a temporary measure both DM and non-DM uses are supported. Once all the users have been converted the non-DM support can be dropped. Signed-off-by: Chris Packham <judge.packham@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26net: mvgbe: prepare for conversion to driver modelChris Packham
Extract some function bodies to helper functions that can be reused in the DM/non-DM implementations. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26sandbox: eth-raw: Add a SIMPLE_BUS to enumerate host interfacesJoe Hershberger
Ask the OS for each of its interfaces and for each one, bind a U-Boot device and then probe it. This will allocate the priv data structure that is then populated. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26sandbox: eth-raw: Make random MAC addresses available to eth-rawJoe Hershberger
We don't necessarily know how many MAC addresses we'll need, so implement a ROM read so we always have something valid. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26sandbox: eth-raw: Allow interface to be specified by indexJoe Hershberger
With systemd stable interface names, eth0 will almost never exist. Instead of using that name in the sandbox.dts, use an index. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26sandbox: eth-raw: Add a function to ask the host about localhostJoe Hershberger
Instead of doing a simple string compare against "lo", look for the flag that indicates a localhost interface. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26net: sandbox-raw: Convert raw eth driver to livetreeJoe Hershberger
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26net: sandbox: Convert sandbox mock eth driver to livetreeJoe Hershberger
Use the dev_ functions to access DT properties. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26net: Correct comment in KconfigJoe Hershberger
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-23eth: dm: fec: Add gpio phy reset bindingMichael Trimarchi
Add the missing gpio phy reset binding to the gpio and reset time configuration Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-16net: sun8i-emac: support R40 GMACLothar Felten
Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16net: sun8i-emac: set mux and clock by driver dataLothar Felten
Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2018-07-16net: sun8i-emac: fix printing NULL characterLothar Felten
If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-09net: designware: Add reset ctrl to driverLey Foon Tan
Add code to reset all reset signals as in Ethernet DT node. A reset property is an optional feature, so only print out a warning and do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-02net: mvneta: zero Tx descriptors on initRabeeh Khoury
Make the initialization sequence consistent with the Linux kernel driver. Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2018-07-02net: mvneta: dcache flush TX descriptors at initRabeeh Khoury
This fixes sporadic timeout on initial packet Tx (usually ARP), with an error message like: timeout: packet not sent Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2018-07-02net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()Michal Simek
phyread can timeout and val will contain random value. Initialize it to zero not to report random value in case of error. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19net: sh_eth: Support reset GPIO both in mac and phy nodeMarek Vasut
The recent DTs have the PHY reset GPIO in the PHY node rather than the ethernet MAC node, support extracting the PHY reset GPIO info from both the PHY node and ethernet MAC node. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19net: ravb: Support reset GPIO both in mac and phy nodeMarek Vasut
The recent DTs have the PHY reset GPIO in the PHY node rather than the ethernet MAC node, support extracting the PHY reset GPIO info from both the PHY node and ethernet MAC node. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19net: ravb: Filter out supported PHY featuresMarek Vasut
The RAVB only supports 100Full and 1000Full operation, it does not support 10Full or any Half-duplex modes. The PHY could still advertise those features though, so filter out the PHY features accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19net: ravb: Do not shut down clock in start callbackMarek Vasut
Do not stop the clock in the start callback in case of failure, keep them running to also keep the PHY running. The failure could be ie. PHY failing to negotiate link and if the clock get shut down, another attempt at bringing the link up would fail. The clock right now are started in probe function and stopped in remove function, which is the correct behavior. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: gem: Check return value from memalign/mallocMichal Simek
Functions can return NULL in case of error that's why checking return value is needed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: zynq_gem: Initialize phyreg variableMichal Simek
In case of phyread()/phy_setup_op() timeout code is working with uninitialized phyreg variable. Initialize this variable to make sure that code it not working with random value. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: zynq_gem: Fix return type for phy...()Michal Simek
wait_for_bit_le32 returns negative value on failure. Fix phy...() to handle these failures properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: mvgbe: extract common code for SMI waitChris Packham
Combine repeated code from smi_reg_read/smi_reg_write into a common function smi_wait_ready. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: designware: set the PS bit when resetting DMA bus in MII configurationQuentin Schulz
On the SPEAr600 SoC, which has the dwmac1000 variant of the IP block, the DMA reset never succeeds when a MII PHY is used (no problem with a GMII PHY). The designware_eth_init() function sets the DMAMAC_SRST bit in the DMA_BUS_MODE register, and then polls until this bit clears. When a MII PHY is used, with the current driver, this bit never clears and the driver therefore doesn't work. The reason is that the PS bit of the GMAC_CONTROL register should be correctly configured for the DMA reset to work. When the PS bit is 0, it tells the MAC we have a GMII PHY, when the PS bit is 1, it tells the MAC we have a MII PHY. Doing a DMA reset clears all registers, so the PS bit is cleared as well. This makes the DMA reset work fine with a GMII PHY. However, with MII PHY, the PS bit should be set. We have identified this issue thanks to two SPEAr600 platform: - One equipped with a GMII PHY, with which the existing driver was working fine. - One equipped with a MII PHY, where the current driver fails because the DMA reset times out. Note: Taken from https://www.spinics.net/lists/netdev/msg432578.html Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: phy: mv88e61xx: Force CPU port link upChris Packham
When connecting to from a CPU direct to a 88e6097 typically RGMII is used. In order for traffic to actually pass we need to force the link up so the CPU MAC on the other end will see the link. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
generated by cgit (git 2.34.1) at 2024-12-23 23:17:19 +0000