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path: root/drivers/net
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2020-04-06net: zynq-gem: Setup and use mdio base separatelyMichal Simek
Not all IPs have private MDIO bus and MDIO bus should be shared between several IPs. In past one patch tried to implement it (https://lists.denx.de/pipermail/u-boot/2018-February/319285.html) in pretty raw way but it is not the cleanest solution. This patch is just taking the part of that solution to be able to handle it over releases without conflicts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06net: zynq_gem: Add cache flush to zynq_gem_free_pktAshok Reddy Soma
Add cache flush to zynq_gem_free_pkt. This is necessary because some net routines would modify this buffer in place. The cache_invalidate in the zynq_gem_recv function would cause the modifications to the buffer to overwrite the DMA from the GEM, if cache coherency is not enabled in the GEM, the next time the buffer is in use. Flushing the cache when the buffer is no longer in use by the net functions ensures that the GEM DMA is going to take place into a clean buffer. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-04net: sh_eth: Init the hardware before PHY accessMarek Vasut
To access the PHY, the MAC registers must be initialized. Call the init function in probe() to make it so, otherwise the PHY ID readout returns all zeroes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-31net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.Michal Simek
When MACB_ZYNQ is enabled there is compilation warnings drivers/net/macb.c: In function ‘_macb_init’: drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function); did you mean ‘MACB_MCF’? writel((value), (port)->regs + MACB_##reg) ^~~~~ It has been caused by changing macros name by commit below. Fixes: 6c636514d499 ("net: macb: sync header definitions as taken from Linux") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-30armv8/ls1046ardb: RGMII ports require internal delayMadalin Bucur
The correct setting for the RGMII ports on LS1046ARDB is to enable delay on both Rx and Tx so the interface mode used must be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns on Rx internal delay by default and the u-boot does not override that (yet) so in u-boot the interface is functional. In Linux the PHY driver is clearing the Rx delay for the "rgmii-txid" mode and the reception does not work. Changing the RGMII mode to internal delay here ensures that device tree fix-ups for the PHY connection type turn on both Tx and Rx internal delay in Linux. Fixes: cc1aa218f510 ("armv8/ls1046a: RGMII PHY requires internal delay on Tx") Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30armv8/ls1043ardb: RGMII ports require internal delayMadalin Bucur
The correct setting for the RGMII ports on LS1043ARDB is to enable delay on both Rx and Tx so the interface mode used must be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns on Rx internal delay by default and the u-boot does not override that (yet) so in u-boot the interface is functional. In Linux the PHY driver is clearing the Rx delay for the "rgmii-txid" mode and the reception does not work. Changing the RGMII mode to internal delay here ensures that device tree fix-ups for the PHY connection type turn on both Tx and Rx internal delay in Linux. Fixes: 5a78a472f666 ("armv8/ls1043a: RGMII PHY requires internal delay on Tx") Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30net: fman: add support for all RGMII delay modesMadalin Bucur
The RGMII modes that include internal delay were not all properly treated in the memac code. Add support for all RGMII delay modes. Fixes: 111fd19e3b9e ("fm/mEMAC: add mEMAC frame work") Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-09net: phy: marvell: Unify 88E151x series phy_driverClemens Gruber
The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-03-09net: phy: dp83867: Add SGMII mode type switchingMichal Simek
This patch adds ability to switch beetween two PHY SGMII modes. Some hardware, for example, FPGA IP designs may use 6-wire mode which enables differential SGMII clock to MAC. Patch description, dt flags have been done in mainline Linux by commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type") and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09net: phy: Fix overlong PHY timeoutAndre Przywara
Commit 27c3f70f3b50 ("net: phy: Increase link up delay in genphy_update_link()") increased the per-iteration waiting time from 1ms to 50ms, without adjusting the timeout counter. This lead to the timeout increasing from the typical 4 seconds to over three minutes. Adjust the timeout counter evaluation by that factor of 50 to bring the timeout back to the intended value. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50") Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Matthias Brugger <mbrugger@suse.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09drivers: net: phy: aquantia: make it less verboseAlex Marginean
The driver now unconditionally prints some information that's not universally useful. Replace printf with debug. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09drivers: net: phy: aquantia: drop XGMII as a valid system interface protoAlex Marginean
Use either USXGMII or XFI in aquantia_set_proto and drop XGMII as a valid protocol configuration. The PHY doesn't support it, it's just used as an alias for one of the other two protocols. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09phy: Include NC-SI in phy setupSamuel Mendoza-Jonas
Add NC-SI to the usual phy handling. This makes two notable changes: - Somewhat similar to a fixed phy, phy_connect() will create an NC-SI phy if CONFIG_PHY_NCSI is defined. - An early return is added to phy_read() and phy_write() to handle a case like the NC-SI phy which does not define a bus. Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09phy: Add support for the NC-SI protocolSamuel Mendoza-Jonas
This introduces support for the NC-SI protocol, modelled as a phy driver for other ethernet drivers to consume. NC-SI (Network Controller Sideband Interface) is a protocol to manage a sideband connection to a proper network interface, for example a BMC (Baseboard Management Controller) sharing the NIC of the host system. Probing and configuration occurs by communicating with the "remote" NIC via NC-SI control frames (Ethernet header 0x88f8). This implementation is roughly based on the upstream Linux implementation[0], with a reduced feature set and an emphasis on getting a link up as fast as possible rather than probing the full possible topology of the bus. The current phy model relies on the network being "up", sending NC-SI command frames via net_send_packet() and receiving them from the net_loop() loop (added in a following patch). The ncsi-pkt.h header[1] is copied from the Linux kernel for consistent field definitions. [0]: https://github.com/torvalds/linux/tree/master/net/ncsi [1]: https://github.com/torvalds/linux/blob/master/net/ncsi/ncsi-pkt.h Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-02-28net: zynq: Free allocated buffers in case of errorMichal Simek
Driver probe function is called again and again in case of error. Malloc space is getting full which is is reported by: Insufficient RAM for page table: 0x15000 > 0x14000. Please increase the size in get_page_table_size() ### ERROR ### Please RESET the board ### The patch is freeing allocated buffers on error path to avoid panic. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-28net: phy: dp83867: Clean force link good bitMichal Simek
On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which means FORCE_LINK_GOOD is already setup. Origin code was doing write but the new code is doing read/modify/write and keep this bit untouched. That's why ethernet stop to work. The patch is cleaning this bit when PHYCR value is composed. Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards. Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-02-28net: zynq_gem: Use ulong instead of u32 data typeT Karthik Reddy
flush_dcache_range() expects unsigned long in the arguments. Here u32 variable is unable to hold the higher address value when ddr mapped to higher addresses & flushing lower address dchache range instead which is unmapped causing to crash. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-19dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>Masahiro Yamada
The implementation of dma_map_single() and dma_unmap_single() is exactly the same for all the architectures that support them. Factor them out to <linux/dma-mapping.h>, and make all drivers to include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>. If we need to differentiate them for some architectures, we can move the generic definitions to <asm-generic/dma-mapping.h>. Add some comments to the helpers. The concept is quite similar to the DMA-API of Linux kernel. Drivers are agnostic about what is going on behind the scene. Just call dma_map_single() before the DMA, and dma_unmap_single() after it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19dma-mapping: fix the prototype of dma_unmap_single()Masahiro Yamada
dma_unmap_single() takes the dma address, not virtual address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-11Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini
sandbox conversion to SDL2 TPM TEE driver Various minor sandbox video enhancements New driver model core utility functions
2020-02-07eth: mtk-eth: aarch64: fix build warnings on ethernet-driverFrank Wunderlich
building mtk ethernet driver for aarch64 (mt7622) results in warnings/errors "error: cast from pointer to integer of different size" Fixes: 23f17164d9 ("ethernet: MediaTek: add ethernet driver for MediaTek ARM-based SoCs") Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-02-07eth: mtk-eth: add mt7622 support in mediatek eth driverMarkLee
This patch add mt7622 support in mediatek eth driver Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
2020-02-07eth: mtk-eth: add sgmii mode support in mediatek eth driverMarkLee
This patch add sgmii init part for the mediatek SoC that support sgmii mode. It is a must for mt7622. Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Require users of devres to include the headerSimon Glass
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05Merge tag 'rpi-next-2020.04' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - DFU support file operations lager then the default max size - add dfu support to dwc2 for bcm2835 - enable DFU for RPi4 - Fix RPi4 memory map to include the genet device - add driver for the genet ethernet device - enable network support in RPi4 config
2020-01-30net: fix typoFlavio Suligoi
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
2020-01-29net: Add support for Broadcom GENETv5 Ethernet controllerAmit Singh Tomar
The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. There is no publicly available documentation, so this driver is based on the Linux driver. Compared to that the queue management is drastically simplified, also we only support version 5 of the IP and RGMII connections between MAC and PHY, as used on the RPi4. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: heavy cleanup and a few fixes] Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-01-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
Updates and fixes for ls1028a, lx2160a, ls1012a, ls1021a, ls2080a, ls1088a platforms: - lx2-rev2 pcie support, enetc related updates, layerscape-pcie fixes
2020-01-25net: macb: Drop local cache flushVignesh Raghavendra
Now that arch specific dma mapping APIs take care of cache flush/invalidate, drop local cache flush operation. While at that fix dma_unmap_single() call to match new prototype Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-01-24drivers: net: fsl_enetc: fix SXGMII MAC configurationAlex Marginean
Separate MAC and serdes configuration, MAC configuration must be applied at each enetc_start() as FLR clears it. This restores traffic for ENETC interfaces in USXGMII mode. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24drivers: net: fsl_enetc: add write_hwaddr() for LS1028AMichael Walle
The LS1028A SoC is special in the handling of the MAC addresses. We need to write to the IERB version of the PSIPMAR0/1 register. This value will be sampled into the corresponding port PSIPMAR0/1 register if the PCI memory access is enabled. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24drivers: net: fsl_enetc: use write_hwaddr()Michael Walle
Intead of setting the MAC address in enetc_start() use the proper write_hwaddr(). U-Boot takes care of the random MAC address, too. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24drivers: net: fsl_enetc: Pass on primary MAC address to LinuxAlex Marginean
Passes on the primary address used by u-boot to Linux. The code does a DT fix-up for ENETC PFs and sets the primary MAC address in IERB. The address in IERB is restored on ENETC PCI functions at FLR. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-17common: Move hang() to the same header as panic()Simon Glass
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17common: Move clock functions into a new fileSimon Glass
These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-14net: zynq: Add a note about RX_BUF macroMichal Simek
Record note about reducing number of BDs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-10drivers: mcfmii: add dm supportAngelo Durgehello
Add specific dm code, but maintaining this driver as is, so more in the shape of a mii library. Can be moved to dm in a further step. Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-10drivers: fsl_mcdmafec: conversion to dmAngelo Durgehello
Full conversion to dm for all boards, legacy code removed. Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-10drivers: mcffec: conversion to dmAngelo Durgehello
Full conversion to dm for all boards, legacy code removed. Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-10drivers: net: add mcf fec dm Kconfig supportAngelo Durgehello
Add ColdFire fec to Kconfig. Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-06Merge branch 'next'Tom Rini
Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
2019-12-26drivers/fsl-mc: Support DPSPARSER object and apply spb commandFlorinel Iordache
Add support for DPSPARSER object (create/destroy, open/close, apply spb) which is required to configure Soft Parser by using MC. Also add uboot command to apply Soft Parser Blob with command: fsl_mc apply spb <spb_load_addr> Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-20drivers: net: bcm-sf2: pass -1 to phy_connect()Alex Marginean
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or is scanning the bus, passing -1 here should keep it functional either way. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Cc: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-20net: dwc_eth_qos: Pass -1 to phy_connect() to scan for all PHYsMarek Vasut
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to phy_connect(). Passing 0 used to work before be accident, but does no longer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-15dm: gpio: Allow control of GPIO uclass in SPLSimon Glass
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09net: ti: am65-cpsw-nuss: Add new compatible for J721eVignesh Raghavendra
Add new compatible to handle J721e SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09net: ti: am65-cpsw-nuss: Rework RX flow ID handlingVignesh Raghavendra
Get flow ID information for RX DMA channel using dma_get_cfg() interface instead of reading from DT. This is required in order to avoid DT update whenever there is change in the range of flow ID allocated to the host. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09net: ftgmac100: align RX/TX descriptors on ARCH_DMA_MINALIGNCédric Le Goater
Fixes: e766849713ff ("net: ftgmac100: convert the RX/TX descriptor arrays") Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: fsl_enetc: register internal MDIO busAlex Marginean
This bus is used to access internal SoC PHYs. These PHYs are configured by the ENETC driver directly, but it's useful to have command line access to this MDIO to debug the system especially when using new external PHYs. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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