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path: root/drivers/net
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2018-07-23eth: dm: fec: Add gpio phy reset bindingMichael Trimarchi
Add the missing gpio phy reset binding to the gpio and reset time configuration Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-16net: sun8i-emac: support R40 GMACLothar Felten
Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16net: sun8i-emac: set mux and clock by driver dataLothar Felten
Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2018-07-16net: sun8i-emac: fix printing NULL characterLothar Felten
If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-09net: designware: Add reset ctrl to driverLey Foon Tan
Add code to reset all reset signals as in Ethernet DT node. A reset property is an optional feature, so only print out a warning and do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-02net: mvneta: zero Tx descriptors on initRabeeh Khoury
Make the initialization sequence consistent with the Linux kernel driver. Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2018-07-02net: mvneta: dcache flush TX descriptors at initRabeeh Khoury
This fixes sporadic timeout on initial packet Tx (usually ARP), with an error message like: timeout: packet not sent Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2018-07-02net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()Michal Simek
phyread can timeout and val will contain random value. Initialize it to zero not to report random value in case of error. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19net: sh_eth: Support reset GPIO both in mac and phy nodeMarek Vasut
The recent DTs have the PHY reset GPIO in the PHY node rather than the ethernet MAC node, support extracting the PHY reset GPIO info from both the PHY node and ethernet MAC node. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19net: ravb: Support reset GPIO both in mac and phy nodeMarek Vasut
The recent DTs have the PHY reset GPIO in the PHY node rather than the ethernet MAC node, support extracting the PHY reset GPIO info from both the PHY node and ethernet MAC node. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19net: ravb: Filter out supported PHY featuresMarek Vasut
The RAVB only supports 100Full and 1000Full operation, it does not support 10Full or any Half-duplex modes. The PHY could still advertise those features though, so filter out the PHY features accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19net: ravb: Do not shut down clock in start callbackMarek Vasut
Do not stop the clock in the start callback in case of failure, keep them running to also keep the PHY running. The failure could be ie. PHY failing to negotiate link and if the clock get shut down, another attempt at bringing the link up would fail. The clock right now are started in probe function and stopped in remove function, which is the correct behavior. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: gem: Check return value from memalign/mallocMichal Simek
Functions can return NULL in case of error that's why checking return value is needed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: zynq_gem: Initialize phyreg variableMichal Simek
In case of phyread()/phy_setup_op() timeout code is working with uninitialized phyreg variable. Initialize this variable to make sure that code it not working with random value. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: zynq_gem: Fix return type for phy...()Michal Simek
wait_for_bit_le32 returns negative value on failure. Fix phy...() to handle these failures properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: mvgbe: extract common code for SMI waitChris Packham
Combine repeated code from smi_reg_read/smi_reg_write into a common function smi_wait_ready. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: designware: set the PS bit when resetting DMA bus in MII configurationQuentin Schulz
On the SPEAr600 SoC, which has the dwmac1000 variant of the IP block, the DMA reset never succeeds when a MII PHY is used (no problem with a GMII PHY). The designware_eth_init() function sets the DMAMAC_SRST bit in the DMA_BUS_MODE register, and then polls until this bit clears. When a MII PHY is used, with the current driver, this bit never clears and the driver therefore doesn't work. The reason is that the PS bit of the GMAC_CONTROL register should be correctly configured for the DMA reset to work. When the PS bit is 0, it tells the MAC we have a GMII PHY, when the PS bit is 1, it tells the MAC we have a MII PHY. Doing a DMA reset clears all registers, so the PS bit is cleared as well. This makes the DMA reset work fine with a GMII PHY. However, with MII PHY, the PS bit should be set. We have identified this issue thanks to two SPEAr600 platform: - One equipped with a GMII PHY, with which the existing driver was working fine. - One equipped with a MII PHY, where the current driver fails because the DMA reset times out. Note: Taken from https://www.spinics.net/lists/netdev/msg432578.html Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: phy: mv88e61xx: Force CPU port link upChris Packham
When connecting to from a CPU direct to a 88e6097 typically RGMII is used. In order for traffic to actually pass we need to force the link up so the CPU MAC on the other end will see the link. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13mvebu: neta: align DMA buffersJon Nettleton
This makes sure the DMA buffers are properly aligned for the hardware. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Jon Nettleton <jon@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: add Socionext AVE ethernet driver supportKunihiko Hayashi
Add driver for Socionext AVE ethernet controller that includes MAC and MDIO bus supporting RGMII/RMII modes. The driver behaves the ethernet driver model (DM_ETH) with devicetree. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13drivers/net/vsc9953: Initialize action RAM in VCAP complexRadu Bulie
VCAP tables must be initialized even if no advanced classification is used. If no initialization is performed, then ECC error will be observed by the user when the first packet enters the l2switch. The error is marked in MPIC_EISR0 -bit 29 which means - Internal RAM multi-bit ECC error. This patch fixes the aforementioned ECC error by performing the initialization of VCAP tables. Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: cpsw: ti: Reap completed packets before stopping interfaceAlex Kiernan
If you send a final packet just before stopping the interface (e.g. a final ACK as part of the UDP fastboot protocol), then that packet isn't reliably delivered onto the wire. Reap packets prior to stopping the interface to ensure any which are in-flight make it out. Also remove buffer and len from the call to cpdma_process() as we weren't using them on their return. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net/phy/cortina: Add support for CS4223 PHYVicentiu Galanopulo
Add support for Cortina CS4223 10G PHY - As per the CS4223 specs, an EEPROM module is connected to the PHY. At startup the PHY reads the firmware line and tries to load the firmware into the internal memory. - This driver reads the EEPROM status and checks if firmware has been loaded Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: sunxi: Correct MAC address register orderJoe Hershberger
Put the enetaddr data in the same order as it was before the change in commit ace1520cb5fc ("net: sunxi-emac: Write HW address via function") Reported-by: Udo Maslo <u.maslo@web.de> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13tsec: Fix reading phy registers from DTMario Six
Bus translations should be applied when reading the address of the sgmii phy registers from the DT. Use ofnode_get_addr_index instead of the plain ofnode_read_u32_default to fix this. Signed-off-by: Mario Six <mario.six@gdsys.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-11LS1012AFRWY: Add Secure Boot supportVinitha V Pillai
Added the following: 1. defconfig for LS1012AFRWY Secure boot 2. PfE Validation support Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-06-02Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
2018-06-01net: ravb: Add R8A77990 E3 compatibleMarek Vasut
Add new compatible to the Ethernet AVB driver for R8A77990 E3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-29net: ftmac100: Fix compiler warningRick Chen
Fix warnings as below when compile in 64-bit. warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
2018-05-23net: Drop CONFIG_TSI108_ETHTuomas Tynkkynen
Last user of this driver went away in June 2015 in commit d928664f4101e24 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support") Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-05-17net: MVGBE don't automatically select PHYLIBChris Packham
When Kconfig support was added for MVGBE it included automatically selected PHYLIB support. But MVGBE does not need PHYLIB it will build fine without it. Commit ed52ea507f12 ("net: add Kconfig for MVGBE") should have been a no-op in terms of build size but because of the selecting PHYLIB the openrd configs increased in size. Remove the automatic selection of PHYLIB, boards that need it will have already enabled it in their config header file. Fixes: commit ed52ea507f12 ("net: add Kconfig for MVGBE") Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14net: add Kconfig for MVGBEChris Packham
Add Kconfig for MVGBE and update boards to select this. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2018-05-14net: mvgbe: remove CONFIG_DOVEChris Packham
Nothing defines CONFIG_DOVE so remove the code that uses it. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-14net: mvneta: Fix fault when wrong device treeMarek Behún
The driver does not check id phy_connect failed (for example on wrong property name in device tree). In such a case a fault occurs and the CPU is restarted. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-11Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2018-05-10SPDX: Convert a few files that were missed beforeTom Rini
As part of the main conversion a few files were missed. These files had additional whitespace after the '*' and before the SPDX tag and my previous regex was too strict. This time I did a grep for all SPDX tags and then filtered out anything that matched the correct styles. Fixes: 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style") Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-09driver: net: fsl-mc: updated copyright infoYogesh Gaur
Updated copyright info for the issues reported after running check-legal test. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-30Merge git://git.denx.de/u-boot-imxTom Rini
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Convert CONFIG_SPI to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_SPI This partly involves updating code that assumes that CONFIG_SPI implies things that are specific to the MPC8xx SPI driver. For now, just update the CONFIG tests. This also involves reworking the default for CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a reasonable default, as it does not cause any compile failures. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-26dts: dm: fec: imx53: Provide proper compatible string for imx53 fec driverLukasz Majewski
After this change the DM FEC ETH driver can be also reused on some imx53 devices. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-04-26eth: dm: fec: Change FEC PHY mask setting from CONFIG_PHYLIB to ↵Lukasz Majewski
CONFIG_FEC_MXC_PHYADDR Without this commit we do have an explicit dependency on CONFIG_PHYLIB when one wants to set PHY ADDR on a iMX board (FEC + driver model). This shall be changed to CONFIG_FEC_MXC_PHYADDR, as only when we do have it set, we shall mask out other devices. As a side effect, when CONFIG_FEC_MXC_PHYADDR is not set, we scan PHY bus for connected PHY devices. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-04-13net: phy: Don't limit phy addresses by defaultJoe Hershberger
Some boards expect to find more than one phy while other boards are old and need to be limited to a specific phy address. Only limit the phy address for boards that opt in. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-13net: sh_eth: Add remaining Gen2 DT compatibleMarek Vasut
Add compatible strings for R8A7790, R8A7793 and R8A7794, since the contemporary DTs use those don't have a generic match value. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: zynq_gem: Use max-speed property from dtSiva Durga Prasad Paladugu
Add support to use max-speed property from dt for determining the supported speed. Use 1000Mbps as default. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: fec: Fix issue in DM probe timeoutYe Li
Since the probe function has changed to reset FEC controller prior than setup PHY. If reset FEC controller timeout, the priv->phydev is not initialized, so can't free it. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: fex_mxc: add i.MX6UL/SX/SL compatiblePeng Fan
Add i.MX6UL/SX/SL compatible. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13net: fec: sharing MDIO for two enet controllersPeng Fan
On i.MX6SX, 6UL and 7D, there are two enet controllers each has a MDIO port. But Some boards share one MDIO port for the two enets. So introduce a configuration CONFIG_FEC_MXC_MDIO_BASE to indicate the MDIO port for sharing. In Kconfig, user needs enable CONFIG_FEC_MXC_SHARE_MDIO first to enter the CONFIG_FEC_MXC_MDIO_BASE. To i.MX28, adapt to use the new config Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-13net: fec: set dev->seq to priv->dev_idPeng Fan
To platforms has two enet interface, using dev->seq could avoid conflict. i.MX6UL/ULL evk board net get the wrong MAC address from fuse, eth1 get MAC0 address, eth0 get MAC1 address from fuse. Set the priv->dev_id to device->seq as the real net interface alias id then .fec_get_hwaddr() read the related MAC address from fuse. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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