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2018-12-03net: zynq_gem: Added 64-bit addressing supportVipul Kumar
This patch adds 64-bit addressing support for zynq gem. This means it can perform send and receive operations on 64-bit address buffers. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
2018-11-29Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogicTom Rini
Cleanup and update towards support for Amlogic Meson AXG SoCs : - mmc: meson-gx: Add AXG compatible - net: designware: add meson meson compatibles - Amlogic Meson cleanup for AXG SoC support
2018-11-27spi: Remove unused spi_initJagan Teki
Remove spi_init definition which never used on respective code since from many years. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-26net: designware: add meson meson axg compatibleNeil Armstrong
Add the compatible string for the upcoming Amlogic AXG SoC family. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26net: designware: add meson meson gxbb compatibleNeil Armstrong
Add the compatible string for the Amlogic GXBB SoC family. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-23sun8i_emac: add support for setting EMAC TX/RX delayIcenowy Zheng
Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-05driver: net: ti: keystone_net: switch to use common mdio libGrygorii Strashko
Update TI Keystone 2 driver to re-use common mdio lib. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05driver: net: ti: cpsw: switch to use common mdio libGrygorii Strashko
Update TI CPSW driver to re-use common mdio lib Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05driver: net: ti: introduce common mdio support libraryGrygorii Strashko
All existing TI SoCs network HW have similar MDIO implementation, so introduce common mdio support library which can be reused by TI networking drivers. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05driver: net: ti: cpsw: update to use SPDX identifierGrygorii Strashko
Update to use SPDX license identifier. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05drivers: net: keystone_net: drop non dm codeGrygorii Strashko
Networking support for all TI K2 boards converted to use DM model and CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop unused non DM K2 networking code. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05configs: net: convert DRIVER_TI_KEYSTONE_NET kconfigGrygorii Strashko
Convert DRIVER_TI_KEYSTONE_NET to Kconfig. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05driver: net: consolidate ti's code in separate folderGrygorii Strashko
Add drivers/net/ti/ folder and move all TI's code in this folder for better maintenance. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05net: phy: mscc: add support for VSC8574 PHYQuentin Schulz
The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX, 1000BASE-X and triple-speed copper SFP capable, can communicate with the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and can set the blinking pattern of each of its 4 LEDs, supports SyncE as well as HP Auto-MDIX detection. This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the MAC. The VSC8574 has also an internal Intel 8051 microcontroller whose firmware needs to be patched when the PHY is reset. If the 8051's firmware has the expected CRC, its patching can be skipped. The microcontroller can be accessed from any port of the PHY, though the CRC function can only be done through the PHY that is the base PHY of the package (internal address 0) due to a limitation of the firmware. The GPIO register bank is a set of registers that are common to all PHYs in the package. So any modification in any register of this bank affects all PHYs of the package. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: phy: mscc: factorize part of config function for VSC8584Quentin Schulz
Part of the config is common between the VSC8584 and the VSC8574, so to prepare for the upcoming support of VSC8574, use the phy_device.priv pointer that will keep the function that holds code that is PHY-specific and that should be called during config function. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: phy: mscc: add support for VSC8584 PHYQuentin Schulz
The VSC8584 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX, 1000BASE-X and triple-speed copper SFP capable, can communicate with the MAC via SGMII, QSGMII or 1000BASE-X, supports downshifting and can set the blinking pattern of each of its 4 LEDs, supports hardware offloading of MACsec and supports SyncE as well as HP Auto-MDIX detection. This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the MAC. The VSC8584 has also an internal Intel 8051 microcontroller whose firmware needs to be patched when the PHY is reset. If the 8051's firmware has the expected CRC, its patching can be skipped. The microcontroller can be accessed from any port of the PHY, though the CRC function can only be done through the PHY that is the base PHY of the package (internal address 0) due to a limitation of the firmware. The GPIO register bank is a set of registers that are common to all PHYs in the package. So any modification in any register of this bank affects all PHYs of the package. The revA of the VSC8584 PHY (which is not and will not be publicly released) should NOT patch the firmware of the microcontroller or it'll make things worse, the easiest way is just to not support it. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: ftgmac100: Add support for the Aspeed SoCCédric Le Goater
The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits). Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: ftgmac100: add clock supportCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: ftgmac100: handle timeouts when transmittingCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: ftgmac100: convert the RX/TX descriptor arraysCédric Le Goater
Use simple arrays under the device priv structure to hold the RX and TX descriptors and handle memory coherency by invalidating or flushing the d-cache when required. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: ftgmac100: add MDIO bus and phylib supportCédric Le Goater
Implement the MDIO bus read/write functions using the readl_poll_timeout() routine, initialize the bus and scan for the PHY. RGMII and RMII mode are supported. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: ftgmac100: use setbits_le32() in the reset methodCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: ftgmac100: convert to driver modelCédric Le Goater
The driver is based on the previous one and the code is only adapted to fit the driver model. The support for the Faraday ftgmac100 controller is the same with MAC and MDIO bus support for RGMII/RMII modes. Configuration is updated to enable compile again. At this stage, the driver compiles but is not yet functional. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: ftgmac100: use the aligned() macroCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: ftgmac100: use the BIT() macroCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05net: Add MT7628 ethernet driverStefan Roese
This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs (e.g. MT7628 and MT7688), including a minimum setup of the integrated switch. This driver is loosly based on the driver version included in this MediaTek github repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git Tested on the MT7688 LinkIt smart-gateway and on the Gardena-smart-gateway. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Frank Wunderlich <frankwu@gmx.de> Cc: Weijie Gao <hackpascal@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29powerpc: t1040: Correct RCW EC2 settingsBin Meng
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay
Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-24net: fec_mxc: add support for i.MX8XAnatolij Gustschin
Add compatible property and enable the FEC ipg clock when probing on i.MX8X. Add specific function for reading FEC clock rate via clock driver when configuring MII speed register. Allow FEC_MXC selection for i.MX8. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: mvpp2: increase PHY reset pulseBaruch Siach
The default Linux PHY reset delay is 10ms. This is also the requirement for Marvell 88E151x PHYs, which are likely to be used with this Ethernet MAC. Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Stefan Roese <sr@denx.de>
2018-10-24net: mvpp2: fix polarity of PHY reset signalBaruch Siach
The dm_gpio_set_value() call sets the logical level of the GPIO signal. That is, it takes the GPIO_ACTIVE_{LOW,HIGH} property into account. The driver needs to assert the reset, and then deassert it. Not the other way around. Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Stefan Roese <sr@denx.de>
2018-10-24net: dm: fec: Obtain the transceiver type from the DTMartin Fuzzey
The DT property "phy-mode" already provides the transceiver type. Use it so that we do not have to also set CONFIG_FEC_XCV_TYPE Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: dm: fec: Support the phy-supply bindingMartin Fuzzey
Configure the phy regulator if defined by the "phy-supply" DT phandle. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: dm: fec: Fix phy-reset-duration clamping and defaultsMartin Fuzzey
The DT binding says: - phy-reset-duration : Reset duration in milliseconds. Should present only if property "phy-reset-gpios" is available. Missing the property will have the duration be 1 millisecond. Numbers greater than 1000 are invalid and 1 millisecond will be used instead. However the current code: - clamps values greater than 1000ms to 1000ms rather than 1. - does not initialize the delay if the property does not exist (else clause mismatch) - returns an error if phy-reset-gpios is not defined Fix all this and simplify by using dev_read_u32_default() Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: dm: fec: Fix time unit error in phy-reset-durationMartin Fuzzey
The DT binding says that phy-reset-duration is in ms, but the driver currently uses udelay(). Switch to mdelay() to fix this. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: phy: aquantia: autodetect if firmware needs to be loadedJeremy Gebben
If the phy reports a valid firmware version and doesn't indicate a fault, skip loading the firmware. This allows the same image to be used on boards that have firmware storage and those that do not. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: phy: aquantia: add firmware loading supportJeremy Gebben
Aquantia phys have firmware that can be loaded automatically from storage directly attached to the phy or via MDIO commands. Add support for loading firmware from either a file or a raw location on an MMC device. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24configs: migrate CONFIG_PHY_AQUANTIA to KconfigJeremy Gebben
The aquantia driver requires both CONFIG_PHY_GIGE and CONFIG_PHYLIB_10G. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-16net: gem: Do not setup any clock for Xilinx SoC VersalMichal Simek
Xilinx SoC Versal is using fixed clock where setting rate is not supported. That's why workaround the driver till real clock driver is supported. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-12ldpaa_eth.c: Fix warning when PHYLIB is not enabledTom Rini
We need to #ifdef some variables to avoid warning about them being unused. Fixes: 1a048cd65645 ("driver: net: fsl-mc: Add support of multiple phys for dpmac") Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-10driver: net: fsl-mc: Add support of multiple phys for dpmacPankaj Bansal
Till now we have had cases where we had one phy device per dpmac. Now, with the upcoming products (LX2160AQDS), we have cases, where there are sometimes two phy devices for one dpmac. One phy for TX lanes and one phy for RX lanes. to handle such cases, add the support for multiple phys in ethernet driver. The ethernet link is up if all the phy devices connected to one dpmac report link up. also the link capabilities are limited by the weakest phy device. i.e. say if there are two phys for one dpmac. one operates at 10G without autoneg and other operate at 1G with autoneg. Then the ethernet interface will operate at 1G without autoneg. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10driver: net: fsl-mc: initialize dpmac irrespective of phyPankaj Bansal
The dpmac initalization should not depend on phy. As the phy is not necessary to be present for dpmac to function. Therefore, remove dpmac initialization dependency from phy. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10driver: net: fsl-mc: Modify the dpmac link detection methodPankaj Bansal
when there is no phy present for a dpmac, a dummy phy device is created. when we move to multiple phy method, we need to create as many dummy phy devices. Change this method so that we don't need to create dummy phy devices. We always report linkup if no phy is present. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10driver: net: fsl-mc: fix error handing in init_phyPankaj Bansal
if an error occurs during init_phy, we should free the phydev structure which has been allocated by phy_connect. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10driver: net: fsl-mc: remove unused strcture elementsPankaj Bansal
The phydev structure is present in both ldpaa_eth_priv and wriop_dpmac_info. the phydev in wriop_dpmac_info is not being used As the phydev is created based on phy_addr and bus members of wriop_dpmac_info, it is appropriate to keep phydev in wriop_dpmac_info. Also phy_regs is not being used, therefore remove it Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10driver: net: fsl-mc: modify the label namePankaj Bansal
The goto label name is misspelled it should be DPMAC not DPAMC Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10test: eth: Add a test for the target being pingedJoe Hershberger
The target will respond to pings while doing other network handling. Make sure that the response happens and is correct. This currently corrupts the ongoing operation of the device if it happens to be awaiting an ARP reply of its own to whatever serverip it is attempting to communicate with. In the test, add an expectation that the user operation (ping, in this case) will fail. A later patch will address this problem. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10test: eth: Add a test for ARP requestsJoe Hershberger
This tests that ARP requests made to this target's IP address are responded-to by the target when it is doing other networking operations. This currently corrupts the ongoing operation of the device if it happens to be awaiting an ARP reply of its own to whatever serverip it is attempting to communicate with. In the test, add an expectation that the user operation (ping, in this case) will fail. A later patch will address this problem. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10net: sandbox: Add a priv ptr for tests to useJoe Hershberger
Tests need to be able to pass their "unit test state" to the handlers where asserts are evaluated. Add a function that allows the tests to set this private data on the sandbox eth device. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-26 12:29:13 +0000