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path: root/drivers/net
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2016-01-28net: phy: do not read configuration register on resetStefan Agner
When doing a software reset, the reset flag should be written without other bits set. Writing the current state will lead to restoring the state of the PHY (e.g. Powerdown), which is not what is expected from a software reset. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Michael Welling <mwelling@ieee.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
2016-01-27driver: net: fsl-mc: Remove portal id hard-codingPrabhakar Kushwaha
Management Complex firmware 9.0 has fixed the issue of dprc_destroy_container i.e. the used portal is not return to the free pool. Which was resulting in error ethernet driver want to use this portal via either DPL or dynamically in Linux. Hard-coding of portal id is removed. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27driver: net: ldpaa: Add debug info of printing DPMAC statsPrabhakar Kushwaha
Add debug information prints to provide DPMAC statistics - Number of bytes received - Number of received and discard frames - Number of bytes transferred - Number of frames transferred etc. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27driver: net: ldpaa: Increase num of buffers for a poolPrabhakar Kushwaha
Management Complex FW 9.0 set the hardware depletion to be 20 buffers in order to support multiple pools in DPNI. This requires driver to fill the pool with at least 21 to be able to receive frames. So, Increase number of buffers for a pool. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27driver: net: ldpaa: Report back only error frames for txPrabhakar Kushwaha
Management Complex FW 9.0 puts a new requirement to provide Tx confirmation and error queue configuration by calling dpni_set_tx_conf API. Configure report of only error frames for a tx frame. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27driver: net: fsl-mc: Prepare extended cfg for DPNI createPrabhakar Kushwaha
Management Complex FW 9.0 puts a new requirement to prepare extended parameters which should be provided as input in dpni_create. extended parameters includes traffic class and IP reassembly configurations. So prepare extended parameters with default "0" as input for dpni_create. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27driver: net: fsl-mc: flib changes for MC FW 9.0.0Prabhakar Kushwaha
MC firmware version 9.0.0 contains - Support of new APIs - Update in existing APIs - Change in Major and minor version of DPAA2 objects This patch contains modifications in FLIB files to support new MC firmware version. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27driver: net: fsl-mc: Add version check for MC objectsPrabhakar Kushwaha
Check and compare version of management complex's object with the version supported by Freescale ldpaa2 ethernet driver. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27net: xilinx_ll_temac: Fix string overflowRicardo Ribalda Delgado
Size of this snprintf "lltemac.%lx" is bigger than 16 characters. Replacing it with "ll_tem.%lx" Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27net: zynq: Change MDC setup for arm64Michal Simek
MDC setting depends on pclk input clocks which varies across SoC. This driver is used by xilinx zynq and zynqmp SOC. Input clock frequence on silicon is 125MHz where divider 64 put frequency below 2.5MHz requires by spec (125/64=1.95). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27net: phy: ti: Enable automatic crossover modeMichal Simek
Enable automatic crossover cable detection. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Move emaclite to KconfigMichal Simek
Add PHYLIB and MII dependencies and enable it by default for Microblaze. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Let core to handle received packetMichal Simek
Pass pointer to core to handle packet. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27net: emaclite: Rename start and stop functionsMichal Simek
Rename start and stop functions to align with DM functions names. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27net: emaclite: Move driver to DMMichal Simek
Move driver to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Use indirect access in emaclite_recvMichal Simek
When IP is configured with pong buffers, IP is receiving packets to ping and then to pong buffer and than ping again. The original logic in the driver remains there that when ping buffer is free, pong buffer is checked too and return if both are free. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27net: emaclite: Use indirect reg access in sendMichal Simek
The original logic in the driver was exchanging buffers which are used for sending packet and tx_ping and tx_pong buffers were exchanged all the time to ensure that IP has enough time to send the packet out. Based on this "feature" send function was using nextbuffertouse variable to save which buffer should be used. Before this algorithm was called driver checked that there is free buffer available. This checking remains in the driver but driver tries to use tx_ping first if available. If not, tx_pong buffer is used instead. To reach this code the original condition is met that at least one of the buffer should be available. Testing doesn't show any performance drop when this patch is applied. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Remove XEL_TSR_XMIT_ACTIVE_MASK flagMichal Simek
This flag is not documented anywhere in the latest documentation that's why this patch removes it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Fix logic around available TX buffersMichal Simek
Simplify logic how to find out if there is free TX buffer. Both buffers are checked all the time that's why logic around order can be removed. Also add check when only one buffer is available. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Use indirect register access for TX resetMichal Simek
Move to use indirect register access when timeout expires for resetting TX buffers. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Use indirect register access for rx_ping/pongMichal Simek
Do initialization via indirect register access. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27net: emaclite: Use indirect register access for tx_ping/pongMichal Simek
Do initialization via indirect register access. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Convert MDIO to use register offsetMichal Simek
Use u-boot coding style how to setup and access MDIO bus. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Add MDIO support to driverMichal Simek
Add MDIO support before move to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: emaclite: Remove ancient OF probe functionMichal Simek
Prepare for DM move. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: Add axi emac to KconfigMichal Simek
Also add dependency on PHYLIB and MII which is required. Clean PHYLIB dependency from the driver too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: axi_emac: Rename start, stop, write_hwaddr functionsMichal Simek
Rename few functions to fit to the new name convention used by DM. Suggested-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27net: axi_emac: Split recv from free_pktMichal Simek
Call net_process_received_packet() by core. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: axi_emac: Enable access to MDIO in probeMichal Simek
Detect phy when driver probes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: axi_emac: Move driver to DMMichal Simek
Move driver to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: axi_emac: Pass private structure where possibleMichal Simek
Use axidma_priv instead of ethdevice in preparation of the DM move. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27net: axi_emac: Pass private structure to phyread/phywriteMichal Simek
Prepare for move to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: axi_emac: Put iobase to private structureMichal Simek
Saving iobase directly to private structure helps with moving to DM. There is an option to load iobase from pdata but it is additional load. Pointer to private structure is available all the time. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: axi_emac: Pass directly pointer to register spaceMichal Simek
Simplify mdio_wait function by passing regs directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: axi_emac: Show phy address instead of register contentMichal Simek
Fix debug message. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: axi_emac: Fix parentheses around operand !Michal Simek
Fix these compilation warning by proper grouping: In function 'axi_dma_init': drivers/net/xilinx_axi_emac.c:391:7: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses] if (!(in_be32(&priv->dmatx->control) | ^ In function 'axiemac_send': drivers/net/xilinx_axi_emac.c:501:21: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses] while (timeout && (!in_be32(&priv->dmatx->status) & Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27net: macb: Not all the GEM are gigabit capableGregory CLEMENT
During the initialization of PHY the gigabit bit capable is set if the controller is a GEM. However, for sama5d2 and sama5d4, the GEM is configured to support only 10/100. Improperly setting the GBE capability leads to an unresponsive MAC controller. This patch fixes this behavior allowing using the gmac with these SoCs. Suggested-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixed minor checkpatch warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-01-25drivers: net: fsl_mc: Compare pointer value qbman_swp_mc_startPratiyush Mohan Srivastava
Current code compares the return pointer of function qbman_cena_write_start with NULL. Instead the value of the return pointer should be compared. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25net: eepro100: Fix build warningsBin Meng
When building katmai, it reports quite a lot warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Fix this by casting the dev->iobase with u_long. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-25bug.h: move BUILD_BUG_* defines to include/linux/bug.hMasahiro Yamada
BUILD_BUG_* macros have been defined in several headers. It would be nice to collect them in include/linux/bug.h like Linux. This commit is cherry-picking useful macros from include/linux/bug.h of Linux 4.4. I did not import BUILD_BUG_ON_MSG() because it would not work if it is used with include/common.h in U-Boot. I'd like to postpone it until the root cause (the "error()" macro in include/common.h causes the name conflict with "__attribute__((error()))") is fixed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-25net: zynq_gem: Use shared wait_for_bitMateusz Kulikowski
Use existing library function to poll bit(s). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
2016-01-16net: pcnet: refactor mapping of virtual addresses to physical onesDaniel Schwierzeck
pci_virt_to_mem() uses virt_to_phys() to get the physical address. But pci_virt_to_mem() is also called with uncached addresses which is wrong according to the documentation of virt_to_phys(). Refactor the PCI_TO_MEM() macro to optionally map an uncached address back to a cached one before calling pci_virt_to_mem(). Currently pcnet works because virt_to_phys() is incorrectly implemented on MIPS. With the upcoming asm header file update for MIPS, the virt_to_phys() implementation will be fixed. Thus this patch is needed to keep pcnet working on MIPS Malta board. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-14Fix GCC format-security errors and convert sprintfs.Ben Whitten
With format-security errors turned on, GCC picks up the use of sprintf with a format parameter not being a string literal. Simple uses of sprintf are also converted to use strcpy. Signed-off-by: Ben Whitten <ben.whitten@gmail.com> Acked-by: Wolfgang Denk <wd@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14Merge git://www.denx.de/git/u-boot-marvellTom Rini
Conflicts: arch/arm/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-14net: mvneta: Convert to driver modelStefan Roese
Update this driver to support driver model. As all MVEBU boards using this driver are converted with this patch, the non-driver-model code can be removed completely. This is also the reason why this patch is quite big and includes a) the driver change and b) the platform change. As its not git-bisect save otherwise. With this conversion, some parameters are now extracted from the DT instread of using the config header defines. The supported properties right now are: PHY-mode ("phy-mode") and PHY-address ("reg"). The base addresses for the ethernet controllers can be removed from the header files as well. Please note that this patch also removes the E1000 network driver from some MVEBU config headers. This is necessary, as with DM_ETH configured and the e1000 driver enabled, the PCI driver also needs to support DM. But the MVEBU PCI(e) driver still needs to get ported to DM. When this is done, the E1000 driver can be enabled again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Simon Glass <sjg@chromium.org>
2016-01-13net: lpc32xx: fix ignored MDIO busy wait status on readVladimir Zapolskiy
The change fixes PHY write operation, which incorrectly waits for released busy state before issuing a write operation, this breaks sequential write/read operation logic, because read operation starts immediately on request and it completes, when busy state is gone. Instead of adding the second preceding busy state check to read function, do busy state release check after issuing a write operation, this method of operation is also recommended by the LPC32xx User's Manual, see MII Mgmt Indicators Register notes: For PHY Write if scan is not used: 1. Write 0 to MCMD 2. Write PHY address and register address to MADR 3. Write data to MWTD 4. Wait for busy bit to be cleared in MIND Reported-by: Alexandre Messier <amessier@tycoint.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Alexandre Messier <amessier@tycoint.com>
2016-01-13block: pass block dev not num to read/write/erase()Stephen Warren
This will allow the implementation to make use of data in the block_dev structure beyond the base device number. This will be useful so that eMMC block devices can encompass the HW partition ID rather than treating this out-of-band. Equally, the existence of the priv field is crying out for this patch to exist. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-13Merge git://git.denx.de/u-boot-netTom Rini
2016-01-12dm: net: Convert rtl8169 to use DM PCI APISimon Glass
Update this driver to use the proper driver-model PCI API functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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